PIC18F25J10-I/SO Microchip Technology, PIC18F25J10-I/SO Datasheet - Page 327

• Manufacturer Part Number: PIC18F25J10-I/SO
• Description: IC PIC MCU FLASH 16KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/I2C/MSSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 23-18:
TABLE 23-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 23-19:
TABLE 23-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
© 2007 Microchip Technology Inc.
120
121
122
Param.
125
126
Param
No.
No.
Note:
RX/DT
TX/CK
T
T
T
Note:
T
T
CK
CKRF
Symbol
DTRF
RX/DT
TX/CK
CK
Symbol
DT
pin
pin
H2
L2
V2
pin
pin
DT
DTL
CKL
Refer to Figure 23-3 for load conditions.
V SYNC XMIT (MASTER and SLAVE)
Refer to Figure 23-3 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER and SLAVE)
Data Hold before CK ↓ (DT hold time)
Data Hold after CK ↓ (DT hold time)
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
Preliminary
121
PIC18F45J10 FAMILY
126
Min
10
15
Min
Max
—
—
—
—
—
122
Units
Max
ns
ns
40
20
20
Units
ns
ns
ns
DS39682C-page 325
Conditions
Conditions