PIC18F65J15T-I/PT Microchip Technology, PIC18F65J15T-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F65J15T-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J15T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18F65J15T-I/PT; PIC18F65J15T-I/PTTR

5. Module: MSSP
6. Module: MSSP (SPI Mode)
FIGURE 1:
© 2006 Microchip Technology Inc.
After an I
register may be written for up to 10 T
additional writes are blocked. The data transfer may
be corrupted if SSPxBUF is written during this time.
The WCOL bit is set any time an SSPxBUF write
occurs during a transfer.
Work around
Avoid writing SSPxBUF until the data transfer is
complete, indicated by the setting of the SSP1IF
bit (PIR1<3>).
Verify the WCOL bit (SSPxCON1<7>) is clear after
writing SSPxBUF to ensure any potential transfer
in progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCKx pulse may
occur on the first bit of the transmitted/received
data (Figure 1).
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPxBUF
with the data to transmit and then turn Timer2 back
on. Refer to Example 2 for sample code.
SDOx
SCKx
Write SSPxBUF
2
C transfer is initiated, the SSPxBUF
bit 7 = 1 bit 6 = 0
SCKx PULSE VARIATION
USING TIMER2/2
bit 5 = 1
. . . .
CY
before
PIC18F87J10 FAMILY
EXAMPLE 2:
7. Module: MSSP
LOOP BTFSS SSP1STAT, BF
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the SDOx output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCKx.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
BRA
MOVF
MOVWF RXDATA
MOVF
BCF
CLRF
MOVWF SSP1BUF
BSF
LOOP
SSP1BUF, W
TXDATA, W
T2CON, TMR2ON
TMR2
T2CON, TMR2ON
AVOIDING THE INITIAL
SHORT SCK1 PULSE
(FOR MSSP1)
;Data received?
;(Xmit complete?)
;No
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Timer2 off
;Clear Timer2
;Xmit New data
;Timer2 on
DS80246B-page 3