PIC18F65J15T-I/PT Microchip Technology, PIC18F65J15T-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F65J15T-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J15T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18F65J15T-I/PT; PIC18F65J15T-I/PTTR

PIC18F87J10 FAMILY
4. Module: Timer1
5. Module: Master Synchronous Serial Port
TABLE 1:
DS80340B-page 2
Note 1:
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increment and set the interrupt
flags as expected and the Timer registers can be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
2. Use the internal clock synchronization option
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the following bits are not reset upon
disabling the SPI module (by clearing the SSPEN
bit in SSPxCON1 register):
• Buffer Full bit – BF in SSPxSTAT register
• Write Collision Detect bit – WCOL in
• Receive Overflow Indicator bit – SSPOV in
For example, if SSPxBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, that can
mean:
• A subsequent write to SSPxBUF will result in a
• A new byte will cause a receive overflow
SSPxCON1
SSPxCON1
write collision
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
(T1CON<7>).
by clearing the T1SYNC bit (T1CON<2>).
4 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
(MSSP)
I
2
2
C™ interface does not conform to the 400 kHz I
C™ CLOCK RATE with BRG
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
6. Module: Master Synchronous Serial Port
2
Note:
C specification (which applies to rates greater than
Work around
Before disabling the MSSP module, ensure that:
• WCOL is clear
• If the buffer is full, SSPxBUF is read (thus
• If the module was configured in SPI Slave
Date Codes that pertain to this issue:
All engineering and production devices.
In its current implementation, the Baud Rate Gen-
erator for I
rates specified in Table 19-3 of the Device Data
Sheet.
For this revision of silicon:
• For the I
• For bit description, SSPM<3:0> = 1000, use
Date Codes that pertain to this issue:
All engineering and production devices.
clearing the BF flag)
mode, the SSPOV bit is clear
shown in Table 1 in place of those shown in
Table 19-3 of the Device Data Sheet. (The
differences are shown in bold text.)
the following formula in place of the one shown
in Register 18-2 (SSPxCON1) of the Device
Data Sheet.
SSPADD = INT((F
The I
the accuracy of the bus frequency is not
critical.
BRG Value
2
2
(MSSP)
C™ in Master mode is slower than the
C™ clock rates – use the values
2
0Eh
15h
59h
05h
08h
23h
01h
08h
00h
C bus is a synchronous protocol, so
 2010 Microchip Technology Inc.
CY
/F
SCL
) – (F
(2 Rollovers of BRG)
CY
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
/1.111 MHz)) – 1
F
SCL
(1)
(1)
(1)
(1)