PIC12C672-10I/MF Microchip Technology, PIC12C672-10I/MF Datasheet - Page 450
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PIC12C672-10I/MF
Manufacturer Part Number
PIC12C672-10I/MF
Description
IC MCU OTP 2KX14 A/D 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-10I/MF
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
PIC12C67210I/MF
- Current page: 450 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
24.3.1
DS31024A-page 24-8
Slope A/D Timer (ADTMR)
The Slope A/D timer (ADTMR) is comprised of a 16-bit timer (ADTMRH:ADTMRL), which is
incremented every oscillator cycle. The ADTMR registers are cleared by a power-on reset; oth-
erwise the software must initialize it after each conversion. A separate 16-bit capture register
(ADCAPH:ADCAPL) is used to capture the ADTMR count if a Slope A/D capture event occurs
(see below). Both the Slope A/D timer and capture registers are readable and writable. The 16-bit
timer is a read/write register and is cleared on any device reset.
During a conversion one or both of the following events will occur:
• capture event
• timer overflow
In a capture event, the comparator trips when the slope voltage on the CDAC output exceeds the
input voltage from the selected Slope A/D channel, causing the comparator output to transition
from high to low. This causes a transfer of the current timer count to the capture register and sets
the ADCIF flag bit.
An interrupt will be generated if the ADCIE bit is set (interrupt enabled). In addition, GIE and PIE
bits must be set. Software is responsible for clearing the ADCIF flag bit prior to the next conver-
sion cycle. This interrupt can only occur once per conversion cycle.
In a timer overflow condition, the timer rolls over from FFFFh to 0000h, and a capture overflow
flag (OVFIF) is asserted. The timer continues to increment following a timer overflow. An interrupt
can be generated if bit OVFIE is set (interrupt enabled). In addition, the GIE and PIE bits must
be set. Software is responsible for clearing the OVFIF flag bit prior to the next conversion cycle.
Figure 24-2: Example Slope A/D Conversion Cycle
Note 1: Reading or writing the ADTMR register during an Slope A/D conversion cycle can
Note 2: The correct sequence for writing the ADTMR register is HI byte followed by LO byte.
produce unpredictable results and is not recommended.
Reversing this order will prevent the Slope A/D timer from running.
CAPTURE
CLK
ADRST
ADCON0<1>
CDAC
ADCIF
Capture
Register
ADTMR
COUNT
(must be cleared by software)
XX
ADTMR INCREMENTS
XX+1 XX+2 XX+3
XX
XX+8 XX+9
1997 Microchip Technology Inc.
COMPARE
XX+8
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