ATTINY24-20SSU Atmel, ATTINY24-20SSU Datasheet - Page 154

• Manufacturer Part Number: ATTINY24-20SSU
• Description: IC MCU AVR 2K FLASH 20MHZ 14SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-20SSU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3
18.4
154
Performing a Page Write
Addressing the Flash During Self-Programming
ATtiny24/44/84
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
Note:
The Z-pointer is used to address the SPM commands.
Since the Flash is organized in pages (see
be treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in
are addressed independently. Therefore it is of major importance that the software addresses
the same page in both the Page Erase and Page Write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Figure 18-1. Addressing the Flash During SPM
Note:
Bit
ZH (R31)
ZL (R30)
Z - REGISTER
The CPU is halted during the Page Write operation.
The variables used in
PROGRAM MEMORY
BIT
PAGE
PROGRAM
COUNTER
15
Figure 19-1 on page
Z15
15
Z7
7
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
PCMSB
Z14
Z6
14
6
Figure 18-1
PCPAGE
Z13
13
Z5
5
163. Note that the Page Erase and Page Write operations
are listed in
ZPAGEMSB
PAGEMSB
Table 19-8 on page
PCWORD
Z12
12
Z4
4
WORD ADDRESS
WITHIN A PAGE
Table 19-8 on page
1
Z11
0
0
11
Z3
3
INSTRUCTION WORD
PAGE
Z10
10
Z2
2
162), the Program Counter can
162.
Z9
Z1
9
1
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Z8
Z0
8
0
8006K–AVR–10/10