PIC16LC717-I/SO Microchip Technology, PIC16LC717-I/SO Datasheet - Page 86
![IC MCU OTP 2KX14 A/D PWM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LC717-I/SO
Manufacturer Part Number
PIC16LC717-I/SO
Description
IC MCU OTP 2KX14 A/D PWM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC717-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC717I/SO
- Current page: 86 of 220
- Download datasheet (4Mb)
PIC16C717/770/771
9.2.7
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
Refer to Application Note AN578, "Use of the SSP
Module in the I
9.2.8
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
1.
2.
3.
4.
5.
6.
The master device generates all serial clock pulses and
the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START con-
dition. Since the Repeated START condition is also the
beginning of the next serial transfer, the I
be released.
DS41120B-page 84
Note:
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write to the SSPBUF register initiating transmis-
sion of data/address.
Generate a STOP condition on SDA and SCL.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
The MSSP Module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to, and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
MULTI-MASTER OPERATION
I
2
C MASTER OPERATION
2
C™ Multi-Master Environment."
2
C port to receive data.
2
C bus will not
Advance Information
2
2
C
C
9.2.9
The baud rate generator used for SPI mode operation
is used in the I
quency. Standard SCL clock frequencies are 100 kHz,
400 kHz, and 1 MHz. One of these frequencies can be
achieved by setting the SSPADD register to the appro-
priate number for the selected Fosc frequency. One
half of the SCL period is equal to
[(SSPADD+1) 2]/Fosc.
The baud rate generator reload value is contained in
the lower seven bits of the SSPADD register (Figure 9-
14). When the BRG is loaded with this value, the BRG
counts down to 0 and stops until another reload occurs.
The BRG count is decremented twice per instruction
cycle (T
In I
provided that the SCL line is sampled high. For exam-
ple, if Clock Arbitration is taking place, the BRG reload
will be suppressed until the SCL line is released by the
slave allowing the pin to float high (Figure 9-15).
FIGURE 9-14:
2
SSPM<3:0>
C Master mode, the BRG is reloaded automatically
SSPM<3:0>
CY
BRG CLKOUT
) on the Q2 and Q4 clock.
SCL
BAUD RATE GENERATOR
2
C Master mode to set the SCL clock fre-
BAUD RATE GENERATOR
BLOCK DIAGRAM
Control
Reload
2002 Microchip Technology Inc.
BRG Down Counter
SSPADD<6:0>
Reload
Fosc/2
Related parts for PIC16LC717-I/SO
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![PIC16LC71-04I/P](/photos/6/76/67657/18-dip_300mil__tmb.jpg)
Part Number:
Description:
IC MCU OTP 1KX14 A/D 18DIP
Manufacturer:
Microchip Technology
Datasheet:
![PIC16LC71-04I/SO](/photos/6/76/67656/150-18-soic_tmb.jpg)
Part Number:
Description:
IC MCU OTP 1KX14 A/D 18SOIC
Manufacturer:
Microchip Technology
Datasheet:
![PIC16LC71-04/SO](/photos/6/76/67656/150-18-soic_tmb.jpg)
Part Number:
Description:
IC MCU OTP 1KX14 A/D 18SOIC
Manufacturer:
Microchip Technology
Datasheet:
![PIC16LC71-04/P](/photos/6/76/67657/18-dip_300mil__tmb.jpg)
Part Number:
Description:
IC MCU OTP 1KX14 A/D 18DIP
Manufacturer:
Microchip Technology
Datasheet:
![TC1014-2.7VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1014-5.0VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-2.5VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-2.7VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-2.8VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1055-4.0VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
![TC1186-2.5VCT](/images/manufacturer_photos/0/4/440/microchip_technology_inc__tmb.jpg)
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet: