ATTINY2313A-SU Atmel, ATTINY2313A-SU Datasheet - Page 134
ATTINY2313A-SU
Manufacturer Part Number
ATTINY2313A-SU
Description
IC MCU AVR 2K FLASH 20MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313A-SU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Controller Family/series
ATtiny
No. Of I/o's
18
Eeprom Memory Size
128Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY2313A-SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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14.8.3
134
ATtiny2313A/4313
Asynchronous Operational Range
Figure 14-7
of the next frame.
Figure 14-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table
bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
Table 14-2
that Normal Speed mode has higher toleration of baud rate variations.
F
M
slow
14-2) base frequency, the Receiver will not be able to synchronize the frames to the start
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
R
slow
and
shows the sampling of the stop bit and the earliest possible beginning of the start bit
Sum of character size and parity size (D = 5 to 10 bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. R
accepted in relation to the receiver baud rate.
=
M
Table 14-3
= 5 for Double Speed mode.
------------------------------------------ -
S 1
–
Figure
(
D
+
1
1
+
D S ⋅
1
2
14-7. For Double Speed mode the first low level must be delayed to
list the maximum receiver baud rate error that can be tolerated. Note
)S
+
3
2
S
F
4
fast
5
3
is the ratio of the fastest incoming data rate that can be
6
7
4
8
STOP 1
9
5
10
R
fast
(A)
0/1
6
=
0/1
F
-----------------------------------
(
= 8 for normal speed and S
D
M
(B)
0/1
0/1
(
+
= 9 for normal speed and
D
1
+
)S
2
)S
+
S
M
(C)
8246A–AVR–11/09
F
= 4
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