PIC16C771-I/SO Microchip Technology, PIC16C771-I/SO Datasheet - Page 96
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PIC16C771-I/SO
Manufacturer Part Number
PIC16C771-I/SO
Description
IC MCU OTP 4KX14 A/D PWM 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C771-I/SO
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
15
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Controller Family/series
PIC16C
No. Of I/o's
16
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16C771I/SO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PIC16C717/770/771
9.2.17
Multi-master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, bus arbitration is initiated when one mas-
ter outputs a ’1’ on SDA (by letting SDA float high) and
another master asserts a ’0’. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master that
expected a ‘1’ will set the Bus Collision Interrupt Flag,
BCLIF, and reset the I
(Figure 9-23).
A bus collision during transmit results in the following
events:
• The transmission is halted.
• The BF flag is cleared
• The SDA and SCL lines are de-asserted
• The restriction on writing to the SSPBUF during
When the user services the bus collision interrupt ser-
vice routine, and if the I
resume communication by asserting a START condi-
tion.
FIGURE 9-23:
DS41120B-page 94
transmission is lifted.
SDA
SCL
BCLIF
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
2
2
C bus is free, the user can
C port to its IDLE state.
Data changes
while SCL = 0
Advance Information
SDA released
by master
SDA line pulled low
by another source
A bus collision during a START, Repeated START,
STOP or Acknowledge condition results in the following
events:
• The condition is aborted.
• The SDA and SCL lines are de-asserted.
• The respective control bits in the SSPCON2 regis-
When the user services the bus collision interrupt ser-
vice routine, and if the I
resume communication by asserting a START condi-
tion.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
ter are cleared.
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
2
C bus is free, the user can
2002 Microchip Technology Inc.
2
C