PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 167
![IC PIC MCU FLASH 16KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F45J10-I/PT
Manufacturer Part Number
PIC18F45J10-I/PT
Description
IC PIC MCU FLASH 16KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
7.PIC18F45J10-IPT.pdf
(362 pages)
Specifications of PIC18F45J10-I/PT
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
32
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
40MHz
No. Of Timers
3
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F45J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F45J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F45J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- PIC18F45J10-IPT PDF datasheet #7
- Current page: 167 of 368
- Download datasheet (6Mb)
16.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-Bit Addressing mode and up to
63 addresses in 10-Bit Addressing mode (see
Example 16-2).
The I
address masking is used or not. However, when
address masking is used, the I
Acknowledge multiple addresses and cause interrupts.
When this occurs, it is necessary to determine which
address caused the interrupt by checking SSPxBUF.
In 7-Bit Addressing mode, Address Mask bits,
ADMSK<5:1>
corresponding address bits in the SSPxADD register. For
any ADMSK bits that are set (ADMSK<n> = 1), the cor-
responding address bit is ignored (SSPxADD<n> = x).
EXAMPLE 16-2:
© 2009 Microchip Technology Inc.
7-Bit Addressing:
10-Bit Addressing:
2
SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)
ADMSK<5:1>
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPxADD<7:0>= A0h (10100000) (the two MSbs of the address are ignored in this example, since they are
not affected by masking)
ADMSK<5:1>
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
C Slave behaves the same way, whether
Address Masking
(SSPxCON2<5:1>),
ADDRESS MASKING EXAMPLES
= 00111
= 00111
2
C slave can
mask
the
PIC18F45J10 FAMILY
For the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have an
active address mask.
In 10-Bit Addressing mode, ADMSK<5:2> bits mask
the corresponding address bits in the SSPxADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPxADD<1:0>). For any
ADMSK bits that are active (ADMSK<n> = 1), the cor-
responding address bit is ignored (SSPxADD<n> = x).
Also note that although in 10-Bit Addressing mode, the
upper address bits reuse part of the SSPxADD register
bits, the address mask bits do not interact with those
bits. They only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
DS39682E-page 165
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