PIC18F45J10-E/ML Microchip Technology, PIC18F45J10-E/ML Datasheet - Page 363

• Manufacturer Part Number: PIC18F45J10-E/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Timing Diagrams and Specifications
Top-of-Stack Access .......................................................... 53
TRISE Register
TSTFSZ ........................................................................... 289
Two-Speed Start-up ................................................. 235, 244
Two-Word Instructions
TXSTA Register
© 2009 Microchip Technology Inc.
Transition for Wake From Idle to Run Mode .............. 39
Transition for Wake From Sleep ................................ 38
Transition From RC_RUN Mode to
Transition to RC_RUN Mode ..................................... 37
A/D Conversion Requirements ................................ 335
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 321
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements (CKE = 1) 328
External Clock Requirements .................................. 319
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements ............................ 324
PLL Clock ................................................................. 320
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
PSPMODE Bit .......................................................... 107
Example Cases .......................................................... 57
BRGH Bit ................................................................. 197
2
2
C Bus Data Requirements (Slave Mode) .............. 330
C Bus Start/Stop Bits Requirements
PRI_RUN Mode ................................................. 37
Internal RC Accuracy ....................................... 320
(Including ECCP Module) ................................ 324
Requirements .................................................. 333
Requirements .................................................. 333
(CKE = 0) ................................................. 325, 327
(CKE = 1) ......................................................... 326
(Slave Mode) ................................................... 329
Requirements .................................................. 331
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 322
Requirements .................................................. 323
2
2
C Bus Data Requirements ................ 332
C Bus Start/Stop Bits
PIC18F45J10 FAMILY
V
Voltage Reference Specifications .................................... 316
Voltage Regulator (On-Chip) ........................................... 243
W
Watchdog Timer (WDT) ........................................... 235, 242
WCOL ...................................................... 180, 181, 182, 185
WCOL Status Flag ................................... 180, 181, 182, 185
WWW Address ................................................................ 363
WWW, On-Line Support ...................................................... 6
X
XORLW ........................................................................... 289
XORWF ........................................................................... 290
Associated Registers ............................................... 242
Control Register ....................................................... 242
During Oscillator Failure .......................................... 245
Programming Considerations .................................. 242
DS39682E-page 361