PIC12C671-04I/P Microchip Technology, PIC12C671-04I/P Datasheet - Page 173
PIC12C671-04I/P
Manufacturer Part Number
PIC12C671-04I/P
Description
IC MCU OTP 1KX14 A/D 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C671-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
1
Digital Ic Case Style
DIP
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
1
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (3Mb)
11.4
1997 Microchip Technology Inc.
GIE bit
INSTRUCTION
FLOW
T0IF bit
Instruction
fetched
Instruction
executed
Timer0
CLKOUT(3)
OSC1
PC
TMR0 Interrupt
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
Q1
2: Interrupt latency = 4T
3: CLKOUT is available only in RC oscillator mode.
FEh
Inst (PC)
Inst (PC-1)
Q2
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This
overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE
(INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service rou-
tine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut-off during SLEEP. See
Figure 11-4: TMR0 Interrupt Timing
1
PC
Q3
Q4
CY
Q1
FFh
where T
Inst (PC+1)
Inst (PC)
Q2
1
PC +1
CY
Q3
= instruction cycle time.
Q4
Q1
00h
Dummy cycle
Q2
PC +1
Q3
Section 11. Timer0
Q4
Figure 11-4
Q1
01h
Dummy cycle
Inst (0004h)
Q2
0004h
Q3
for Timer0 interrupt timing.
Q4
Q1
DS31011A-page 11-5
02h
Inst (0004h)
Inst (0005h)
Q2
0005h
Q3
Q4
11
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