PIC16C771-I/SS Microchip Technology, PIC16C771-I/SS Datasheet - Page 35
PIC16C771-I/SS
Manufacturer Part Number
PIC16C771-I/SS
Description
IC MCU OTP 4KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C771-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
15
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16C
No. Of I/o's
16
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP309-1014 - ADAPTER 20-SSOP TO 20-DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16C771I/SS
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3.3
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 3-2:
Each of the PORTB pins has an internal pull-up, which
can be individually enabled from the WPUB register. A
single global enable bit can turn on/off the enabled pull-
ups. Clearing the RBPU bit, (OPTION_REG<7>),
enables the weak pull-up resistors. The weak pull-up is
automatically turned off when the port pin is configured
as an output. The pull-ups are disabled on a Power-on
Reset.
BCF
CLRF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
2002 Microchip Technology Inc.
PORTB and the TRISB Register
STATUS, RP0 ;
PORTB
STATUS, RP0 ; Select Bank 1
0xCF
TRISB
0x30
ANSEL
STATUS, RP0 ; Return to Bank 0
Initializing PORTB
; Initialize PORTB by
; clearing output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
; Set RB<1:0> as analog
;
inputs
Each of the PORTB pins, if configured as input, also
has an interrupt-on-change feature, which can be indi-
vidually selected from the IOCB register. The RBIE bit
in the INTCON register functions as a global enable bit
to turn on/off the interrupt-on-change feature. The
selected inputs are compared to the old value latched
on the last read of PORTB. The "mismatch" outputs are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a)
a)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
PIC16C717/770/771
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
DS41120B-page 33
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