PIC16F639-I/SO Microchip Technology, PIC16F639-I/SO Datasheet - Page 133
PIC16F639-I/SO
Manufacturer Part Number
PIC16F639-I/SO
Description
IC MCU FLASH 2KX14 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC12F635-ISN.pdf
(234 pages)
3.PIC16F636-ISL.pdf
(8 pages)
4.PIC16F636-ISL.pdf
(4 pages)
5.PIC16F639-ISS.pdf
(6 pages)
Specifications of PIC16F639-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LVD, POR, WDT
Number Of I /o
11
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
- PIC16F616T-ISL PDF datasheet
- PIC12F635-ISN PDF datasheet #2
- PIC16F636-ISL PDF datasheet #3
- PIC16F636-ISL PDF datasheet #4
- PIC16F639-ISS PDF datasheet #5
- Current page: 133 of 234
- Download datasheet (4Mb)
12.2
The PIC12F635/PIC16F636/639 differentiates between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Reset
FIGURE 12-1:
© 2007 Microchip Technology Inc.
Note 1:
MCLR/V
Power-on Reset (POR)
Wake-up Reset (WUR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Reset (BOR)
CLKI pin
OSC1/
V
Reset
DD
PP
pin
Refer to the Configuration Word register (Register 12-1).
LFINTOSC
OST/PWRT
Brown-out
V
Module
DD
Detect
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
WDT
Reset
Rise
BOREN<0>
OST
PWRT
SBOREN
(1)
10-bit Ripple Counter
WDT
Time-out
Reset
11-bit Ripple Counter
BOREN
External Reset
Power-on Reset
Sleep
<1>
PIC12F635/PIC16F636/639
Wake-up Interrupt
RA3 Change
They are not affected by a WDT wake-up since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 12-3. These bits are
used in software to determine the nature of the Reset.
See Table 12-4 for a full description of Reset states of
all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 15.0 “Electrical
Specifications” for pulse width specifications.
WURE
Sleep
Enable PWRT
Enable OST
S
R
DS41232D-page 131
Q
Chip_Reset
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