PIC12C672-04I/SM Microchip Technology, PIC12C672-04I/SM Datasheet - Page 150

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PIC12C672-04I/SM

Manufacturer Part Number
PIC12C672-04I/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets

Specifications of PIC12C672-04I/SM

Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
1
Digital Ic Case Style
SOIC
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Data Rom Size
128 B
Height
1.98 mm
Length
5.33 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Width
5.38 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
PICmicro MID-RANGE MCU FAMILY
9.6
DS31009A-page 9-10
PORTE and the TRISE Register
PORTE can be up to an 8-bit port with Schmitt Trigger input buffers. Each pin is individually con-
figurable as an input or output.
Example 9-5: Initializing PORTE
Figure 9-8: Typical PORTE Block Diagram (in I/O Port Mode)
Data Bus
WR PORT
WR TRIS
RD PORT
Note: I/O pins have protection diodes to V
Note:
CLRF
CLRF
BSF
MOVLW
MOVWF
On some devices with PORTE, the upper bits of the TRISE register are used for the
Parallel Slave Port control and status bits.
STATUS
PORTE
STATUS, RP0
0x03
TRISE
TRIS Latch
Data Latch
D
D
CK
CK
; Bank0
; Initialize PORTE by clearing output
;
; Select Bank1
; Value used to initialize data direction
; PORTE<1:0> = inputs, PORTE<7:2> = outputs
Q
Q
Q
Q
RD TRIS
data latches
DD
and V
SS
.
Q
EN
D
1997 Microchip Technology Inc.
Schmitt
Trigger
input
buffer
I/O pin

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