ATTINY45-15SZ Atmel, ATTINY45-15SZ Datasheet - Page 107
ATTINY45-15SZ
Manufacturer Part Number
ATTINY45-15SZ
Description
MCU AVR 4K FLASH 15MHZ 8-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-15MZ.pdf
(196 pages)
Specifications of ATTINY45-15SZ
Package / Case
8-SOIC (3.9mm Width)
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
6
Eeprom Size
256 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
256 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY45-15SZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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7598H–AVR–07/09
Table 16-2
used for the Shift Register and the 4-bit counter.
Table 16-2.
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to
increment by one, provided that the USICS1..0 bits are set to zero and by doing so the software
clock strobe option is selected. The output will change immediately when the clock strobe is exe-
cuted, i.e., in the same instruction cycle. The value shifted into the Shift Register is sampled the
previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independent of the setting in the Data Direction Register, but if the PORT value is
to be shown on the pin the DDRE4 must be set as output (to one). This feature allows easy clock
generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
USICS1
0
0
0
1
1
1
1
shows the relationship between the USICS1..0 and USICLK setting and clock source
USICS0
Relations between the USICS1..0 and USICLK Setting
0
0
1
0
1
0
1
USICLK
X
0
1
0
0
1
1
Shift Register Clock Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, positive edge
External, negative edge
External, positive edge
External, negative edge
Table
16-2).
4-bit Counter Clock Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, both edges
External, both edges
Software clock strobe (USITC)
Software clock strobe (USITC)
ATtiny25/45/85
107
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