PIC18F67J11T-I/PT Microchip Technology, PIC18F67J11T-I/PT Datasheet - Page 8

• Manufacturer Part Number: PIC18F67J11T-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J11T-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 3930Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of Pwm: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F67J11T-I/PTTR

PIC18F87J11 FAMILY
5. Module: Example 6-2: Erasing a Flash
EXAMPLE 6-2:
6. Module: Section 19.3 “SPI Mode” and
DS80495D-page 8
Note:
On page 94, an instruction to enable the write
process to memory for erasing the Flash program-
ming memory row is missing in the example. The
changed content is indicated in bold text in the
following example:
In Section 19.3 “SPI Mode” on page 223 and
Section 19.4 “I
following new note is included to describe the
procedure to disable the MSSPx module:
Required
Sequence
Disabling the MSSPx module by clearing
the SSPEN (SSPxCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSPx module.
ERASE_ROW
Program Memory Row
Section 19.4 “I
2
C™ Mode” on page 233, the
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW CODE_ADDR_UPPER
MOVWF TBLPTRU
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, WREN
BSF EECON1, FREE
BCF INTCON, GIE
MOVLW 55h
MOVWF EECON2
MOVLW 0AAh
MOVWF EECON2
BSF EECON1, WR
BSF INTCON, GIE
2
C™ Mode”
; load TBLPTR with the base
; address of the memory block
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
7. Module: Figure 19-10: I
On page 244, the figure is replaced with the new
timing diagram provided in
Timing (Transmission, 7-Bit
Address)
 2011 Microchip Technology Inc.
Figure
2
C™ Slave Mode
19-10.