PIC16F628-20E/SS Microchip Technology, PIC16F628-20E/SS Datasheet - Page 107
![IC MCU FLASH 2KX14 20-SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F628-20E/SS
Manufacturer Part Number
PIC16F628-20E/SS
Description
IC MCU FLASH 2KX14 20-SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F627-04P.pdf
(170 pages)
Specifications of PIC16F628-20E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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14.9.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the
next instruction (PC + 1) is pre-fetched. For the device
to
FIGURE 14-17:
14.10 Code Protection
If
programmed, the on-chip program memory can be
read out for verification purposes.
2003 Microchip Technology Inc.
Note
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
Note:
the
External RESET input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
wake-up
1: XT, HS or LP Oscillator mode assumed.
2: T
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.
(4)
PC
code
SLEEP
in-line.
The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTRC
calibration data is not erased.
WAKE-UP FROM SLEEP
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
= 1024T
through
Inst(PC - 1)
protection
PC
instruction is being executed, the
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
an
(drawing not to scale). Approximately 1 µs delay will be there for ER Osc mode.
bit(s)
Inst(PC + 1)
SLEEP
PC+1
interrupt
have
Processor in
event,
SLEEP
not
PC+2
been
Preliminary
the
Tost
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
(Note 2)
corresponding interrupt enable bit must be set
(enabled). Wake-up is regardless of the state of the
GIE bit. If the GIE bit is clear (disabled), the device con-
tinues execution at the instruction after the
instruction. If the GIE bit is set (enabled), the device
executes the instruction after the
and then branches to the interrupt address (0004h). In
cases where the execution of the instruction following
SLEEP
after the
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
14.11 User ID Locations
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store
checksum or other code-identification numbers. These
locations are not accessible during normal execution
but are readable and writable during program/verify.
Only the Least Significant 4 bits of the user ID locations
are used.
PC+2
Note:
is not desirable, the user should have an
SLEEP
Dummy cycle
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
PC + 2
instruction.
Inst(0004h)
Dummy cycle
PIC16F62X
0004h
DS40300C-page 105
SLEEP
Inst(0005h)
Inst(0004h)
0005h
instruction
SLEEP
NOP
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