DSPIC30F2012-20E/SP Microchip Technology, DSPIC30F2012-20E/SP Datasheet - Page 20
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DSPIC30F2012-20E/SP
Manufacturer Part Number
DSPIC30F2012-20E/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2012-20E/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- DSPIC30F2011-20ISO PDF datasheet
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- DSPIC30F2011-20IP PDF datasheet #6
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dsPIC30F2011/2012/3012/3013
The core does not support a multi-stage instruction
pipeline. However, a single-stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities ranging from 8 to 15.
2.2
The programmer’s model is shown in
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (ACCA and ACCB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program Coun-
ter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register asso-
ciated with each of them, as shown in
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
• DO instruction
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes (MSB) can be manipulated
through byte-wide data memory space accesses.
DS70139G-page 20
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start and popped on loop end.
Programmer’s Model
Figure
Figure 2-1
2-1. The
and
2.2.1
The dsPIC
W15 is the dedicated Software Stack Pointer (SP),
which
processing and subroutine calls and returns. However,
W15 can be referenced by any instruction in the same
manner as all other W registers. This simplifies the
reading, writing and manipulation of the Stack Pointer
(e.g., creating stack frames).
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer, as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
The dsPIC DSC core has a 16-bit STATUS register
(SR), the LSB of which is referred to as the SR Low
byte (SRL) and the MSB as the SR High byte (SRH).
See
SRL contains all the MCU ALU operation Status flags
(including the Z bit), as well as the CPU Interrupt
Priority Level Status bits, IPL<2:0>, and the Repeat
Active Status bit, RA. During exception processing,
SRL is concatenated with the MSB of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtracter Status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) Status bit.
2.2.3
The program counter is 23 bits wide; bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
Note:
Figure 2-1
is
®
SOFTWARE STACK POINTER/
FRAME POINTER
In order to protect against misaligned
stack accesses, W15<0> is always clear.
STATUS REGISTER
PROGRAM COUNTER
automatically
DSC devices contain a software stack.
for SR layout.
© 2010 Microchip Technology Inc.
modified
by
exception
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