PIC16F870-E/SS Microchip Technology, PIC16F870-E/SS Datasheet - Page 661
![IC MCU CMOS 20MHZ 2K FLSH 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F870-E/SS
Manufacturer Part Number
PIC16F870-E/SS
Description
IC MCU CMOS 20MHZ 2K FLSH 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F870-ISO.pdf
(172 pages)
4.PIC16F870-ISO.pdf
(6 pages)
Specifications of PIC16F870-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
For Use With
I3-DB16F871 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F870-ISO PDF datasheet #3
- PIC16F870-ISO PDF datasheet #4
- Current page: 661 of 688
- Download datasheet (3Mb)
A.4.2
Parameter
Microchip
1997 Microchip Technology Inc.
SCL
SDA
No.
90
91
92
93
Clock Synchronization
T
T
T
T
SU
HD
SU
HD
Sym
:
:
:
:
STA
STO
STA
STO
90
Clock synchronization occurs after the devices have started arbitration. This is performed using
a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the con-
cerned devices to start counting off their low period. Once a device clock has gone low, it will hold
the SCL line low until its SCL high state is reached. The low to high transition of this clock may
not change the state of the SCL line, if another device clock is still within its low period. The SCL
line is held low by the device with the longest low period. Devices with shorter low periods enter
a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start
counting off their high periods. The first device to complete its high period will pull the SCL line
low. The SCL line high time is determined by the device with the shortest high period,
Figure
Figure A-10:
Figure A-11:
Table A-2:
Condition
START
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
A-10.
91
Characteristic
Clock Synchronization
I
I
2
2
C Bus Start/Stop Bits Timing Specification
C Bus Start/Stop Bits Timing Specification
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
SCL
CLK
CLK
1
2
4700
4000
4700
4000
Min
600
600
600
600
counter
reset
state
wait
Typ
—
—
—
—
—
—
—
—
Max
start counting
HIGH period
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
Appendix A
92
Condition
STOP
Only relevant for
repeated START condi-
tion
After this period the first
clock pulse is generated
93
DS31034A-page 34-9
Conditions
34
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