PIC16F648A-I/SO Microchip Technology, PIC16F648A-I/SO Datasheet - Page 106
![IC MCU FLASH 4KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F648A-I/SO
Manufacturer Part Number
PIC16F648A-I/SO
Description
IC MCU FLASH 4KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
5.PIC16F627A-ISO.pdf
(168 pages)
Specifications of PIC16F648A-I/SO
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3DBF648 - BOARD DAUGHTER ICEPIC3AC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F648A-I/SO
Manufacturer:
MICROCHIP
Quantity:
4 500
PIC16F627A/628A/648A
14.5
The PIC16F627A/628A/648A has 10 sources of
interrupt:
• External Interrupt RB0/INT
• TMR0 Overflow Interrupt
• PORTB Change Interrupts (pins RB7:RB4)
• Comparator Interrupt
• USART Interrupt TX
• USART Interrupt RX
• CCP Interrupt
• TMR1 Overflow Interrupt
• TMR2 Match Interrupt
• Data EEPROM Interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on Reset.
The “return from interrupt” instruction,
interrupt routine as well as sets the GIE bit, which re-
enable RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
FIGURE 14-14:
DS40044B-page 104
TMR1IF
TMR1IE
TMR2IF
TMR2IE
CCP1IF
CCP1IE
Interrupts
CMIE
CMIF
RCIF
RCIE
TXIF
TXIE
EEIF
EEIE
INTERRUPT LOGIC
RETFIE
RBIF
RBIE
PEIE
INTF
INTE
T0IF
T0IE
, exits
Preliminary
GIE
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid RB0/
INT recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-
15). The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Note 1: Individual interrupt flag bits are set
2: When an instruction that clears the GIE
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
Wake-up (If in Sleep mode)
2004 Microchip Technology Inc.
Interrupt to CPU
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