PIC18LF25K22-I/SP Microchip Technology, PIC18LF25K22-I/SP Datasheet - Page 125
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF25K22-I/SP
Manufacturer Part Number
PIC18LF25K22-I/SP
Description
MCU 8BIT 32KB FLASH 3.6V 28SDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F26J13-ISS.pdf
(496 pages)
2.PIC18F25K22T-ISS.pdf
(10 pages)
3.PIC18F25K22-ISP.pdf
(492 pages)
Specifications of PIC18LF25K22-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
7
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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REGISTER 9-11:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSP2IE
R/W-0
SSP2IE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR5GIE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR3GIE: TMR3 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR1GIE: TMR1 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE
R/W-0
PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3
W = Writable bit
‘1’ = Bit is set
RC2IE
R/W-0
R/W-0
TX2IE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CTMUIE
R/W-0
PIC18(L)F2X/4XK22
TMR5GIE
R/W-0
x = Bit is unknown
TMR3GIE
R/W-0
DS41412D-page 125
TMR1GIE
R/W-0
bit 0
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