DSPIC30F2010-20E/SP Microchip Technology, DSPIC30F2010-20E/SP Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F2010-20E/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F2010
27. Module: PSV Operations
DS80451E-page 18
An address error trap occurs in certain addressing
modes when accessing the first four bytes of a
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C
Compiler for dsPIC DSCs, version 3.11 or higher,
provides the following command-line switch that
implements a work around for the erratum.
Refer to the readme.txt file in the MPLAB C
Compiler for dsPIC DSCs for further details.
Affected Silicon Revisions
A0
mode) with pre/post-decrement
X
A1
X
-merrata=psv_trap
A2
X
A3
X
A4
X
28. Module: I
29. Module: I
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register I2CxRCV, if the lower address
byte matches the reserved addresses. In particu-
lar, these include all addresses with the form
XX0000XXXX
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
If the I
with an address of 0x102, the I2CxRCV register
content for the lower address byte is 0x01, rather
than
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
A0
A0
X
X
2
0x02.
A1
C module is configured as a 10-bit slave
A1
X
X
2
2
C
C
A2
A2
X
X
However,
and
© 2010 Microchip Technology Inc.
A3
A3
X
X
XX1111XXXX,
A4
A4
X
X
the
I
2
C
with
module
the