PIC18F45K22-I/ML Microchip Technology, PIC18F45K22-I/ML Datasheet - Page 270
![MCU 8BIT 32KB FLASH 5.5V 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F45K22-I/ML
Manufacturer Part Number
PIC18F45K22-I/ML
Description
MCU 8BIT 32KB FLASH 5.5V 44QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F25K22T-ISS.pdf
(10 pages)
Specifications of PIC18F45K22-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
1536Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 28 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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PIC18(L)F2X/4XK22
16.1.2.9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Get the received 8 Least Significant data bits
11. If an overrun occurred, clear the OERR flag by
DS41412D-page 270
Initialize the SPBRGHx:SPBRGx register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
Baud Rate Generator
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
Enable the serial port by setting the SPEN bit
and the RXx/DTx pin TRIS bit. The SYNC bit
must be clear for asynchronous operation.
If interrupts are desired, set the RCxIE interrupt
enable bit and set the GIE/GIEH and PEIE/GIEL
bits of the INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCxIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCxIE interrupt enable bit was also set.
Read the RCSTAx register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
from the receive buffer by reading the RCREGx
register.
clearing the CREN receiver enable bit.
Asynchronous Reception Setup:
Section 16.3 “EUSART
(BRG)”).
Preliminary
16.1.2.10
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read the RCSTAx register to get the error flags.
11. Get the received 8 Least Significant data bits
12. If an overrun occurred, clear the OERR flag by
13. If the device has been addressed, clear the
Initialize the SPBRGHx, SPBRGx register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
Baud Rate Generator
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCxIE interrupt
enable bit and set the GIE/GIEH and PEIE/GIEL
bits of the INTCON register.
Enable 9-bit reception by setting the RX9 bit.
Enable address detection by setting the ADDEN
bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCxIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCxIE interrupt enable
bit was also set.
The ninth data bit will always be set.
from the receive buffer by reading the RCREGx
register. Software determines if this is the
device’s address.
clearing the CREN receiver enable bit.
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
9-bit Address Detection Mode Setup
2010 Microchip Technology Inc.
Section 16.3 “EUSART
(BRG)”).
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