ATMEGA8-16MU Atmel, ATMEGA8-16MU Datasheet - Page 81
![IC AVR MCU 8K 16MHZ 5V 32-QFN](/photos/12/32/123219/atmega8-16mu_sml.jpg)
ATMEGA8-16MU
Manufacturer Part Number
ATMEGA8-16MU
Description
IC AVR MCU 8K 16MHZ 5V 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (6Mb)
Input Capture Unit
2486Z–AVR–02/11
Figure 33. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the High byte temporary register
(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read,
and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows
the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data
bus. It is important to notice that there are special cases of writing to the TCNT1 Register when
the counter is counting that will give unpredictable results. The special cases are described in
the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clk
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare Outputs OC1x. For more details about advanced count-
ing sequences and waveform generation, see
The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by
the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-
tiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit.
count
direction
clear
clk
TOP
BOTTOM
T
1
TCNTnH (8-bit) TCNTnL (8-bit)
TEMP (8-bit)
T
DATA BUS
1
Increment or decrement TCNT1 by 1
Select between increment and decrement
Clear TCNT1 (set all bits to zero)
Timer/Counter clock
Signalize that TCNT1 has reached maximum value
Signalize that TCNT1 has reached minimum value (zero)
is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTn (16-bit Counter)
T
1
). The clk
(8-bit)
T
1
direction
can be generated from an external or internal clock source,
count
clear
Control Logic
“Modes of Operation” on page
TOP
BOTTOM
TOVn
(Int. Req.)
clk
Tn
( From Prescaler )
Clock Select
Detector
Edge
ATmega8(L)
87.
Tn
81
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