ATMEGA16-16AU SL383 Atmel, ATMEGA16-16AU SL383 Datasheet - Page 118
![IC MCU 8BIT 16KB FLASH 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA16-16AU SL383
Manufacturer Part Number
ATMEGA16-16AU SL383
Description
IC MCU 8BIT 16KB FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16L-8MI.pdf
(357 pages)
Specifications of ATMEGA16-16AU SL383
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Definitions
Timer/Counter
Clock Sources
Counter Unit
2466T–AVR–07/10
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC2).
Unit” on page 119.
which can be used to generate an output compare interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used (that is, TCNT2 for accessing
Timer/Counter2 counter value and so on). The definitions in
throughout the document.
Table 49. Definitions
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
chronous Status Register – ASSR” on page
“Timer/Counter Prescaler” on page
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
54
Figure 54. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
count
direction
clear
clk
top
shows a block diagram of the counter and its surrounding environment.
T2
DATA BUS
TCNTn
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal
255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The
assignment is dependent on the mode of operation.
Increment or decrement TCNT2 by 1.
Selects between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock.
Signalizes that TCNT2 has reached maximum value.
for details. The compare match event will also set the Compare Flag (OCF2)
direction
count
clear
bottom
Control Logic
T2
134.
is by default equal to the MCU clock, clk
top
131. For details on clock sources and prescaler, see
TOVn
(Int.Req.)
clk
Tn
Prescaler
Table 49
ATmega16(L)
are also used extensively
Oscillator
See “Output Compare
T/C
I/O
clk
. When the AS2
I/O
TOSC2
TOSC1
“Asyn-
Figure
118
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