AT90PWM3B-16MU Atmel, AT90PWM3B-16MU Datasheet - Page 148

• Manufacturer Part Number: AT90PWM3B-16MU
• Description: IC MCU AVR RISC 8K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3B-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-QFN
• Package: 32QFN EP
• Device Core: AVR
• Family Name: 90P
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 27
• Interface Type: SPI/USART
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 2
• Processor Series: AT90PWMx
• Core: AVR8
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
AT90PWM2/3/2B/3B
DT0
DT0
OT0
OT0
Figure 16-20. PSCn behaviour versus PSCn Input A in Fault Mode 1
PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and
OT1.
When PSC Input A event occurs, PSC releases PSCOUTn0, waits for PSC Input A inactive state
and then jumps and executes DT1 plus OT1.
Figure 16-21. PSCn behaviour versus PSCn Input B in Fault Mode 1
PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.
When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state
and then jumps and executes DT0 plus OT0.
DT1
DT1
OT1
OT1
DT0
DT0
OT0
OT0
DT1
OT1
DT1
OT1
DT0
DT0
OT0
OT0
DT1
DT1
4317J–AVR–08/10
OT1
OT1