PIC18LF2221-I/SS Microchip Technology, PIC18LF2221-I/SS Datasheet - Page 322
![IC PIC MCU FLASH 2KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2221-I/SS
Manufacturer Part Number
PIC18LF2221-I/SS
Description
IC PIC MCU FLASH 2KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/SS
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2221-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- Current page: 322 of 402
- Download datasheet (7Mb)
PIC18F2221/2321/4221/4321 FAMILY
25.2.2
ADDFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39689F-page 322
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
EXTENDED INSTRUCTION SET
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
=
=
ADDFSR 2, 23h
literal ‘k’
Add Literal to FSR
ADDFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
None
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
1
1
Read
1110
Q2
03FFh
0422h
1000
Process
Data
Q3
ffkk
Write to
FSR
kkkk
Q4
ADDULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Operation
Decode
Q1
No
FSR2
PC
FSR2
PC
Add Literal to FSR2 and Return
ADDULNK k
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special
case of the ADDFSR instruction, where
f = 3 (binary ‘11’); it operates only on
FSR2.
1
2
1110
=
=
=
=
Operation
ADDULNK 23h
literal ‘k’
Read
Q2
No
03FFh
0100h
0422h
(TOS)
© 2009 Microchip Technology Inc.
1000
Operation
Process
11kk
Data
Q3
No
Operation
Write to
kkkk
FSR
Q4
No
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