PIC16F83-04/P Microchip Technology, PIC16F83-04/P Datasheet - Page 73

• Manufacturer Part Number: PIC16F83-04/P
• Description: IC MCU FLASH 512X14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F83-04/P

• Core Size: 8-Bit
• Program Memory Size: 896B (512 x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 36Byte
• Cpu Speed: 4MHz
• No. Of: RoHS Compliant
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 36 B
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Data Rom Size: 64 B
• Height: 3.3 mm
• Length: 22.86 mm
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

4.2
1997 Microchip Technology Inc.
OSC2/CLKOUT
(RC mode)
Clocking Scheme/Instruction Cycle
OSC1
Q4
PC
Q2
Q3
Q1
The clock input (from OSC1) is internally divided by four to generate four non-overlapping
quadrature clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incre-
mented every Q1, and the instruction is fetched from the program memory and latched into the
instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow are illustrated in
Example
Figure 4-3: Clock/Instruction Cycle
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
T
4-1.
CY
PC
1
Q3
Q4
Q1
Execute INST (PC)
Fetch INST (PC+1)
Section 4. Architecture
Q2
T
PC+1
CY
2
Q3
Q4
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
T
PC+2
CY
3
Q3
Q4
DS31004A-page 4-5
Figure
Internal
phase
clock
4-3, and
4