ATMEGA16L-8AUR Atmel, ATMEGA16L-8AUR Datasheet - Page 163
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ATMEGA16L-8AUR
Manufacturer Part Number
ATMEGA16L-8AUR
Description
MCU AVR 16KB FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16L-8MI.pdf
(357 pages)
Specifications of ATMEGA16L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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USART Register
Description
USART I/O Data
Register – UDR
2466T–AVR–07/10
The following code example shows how to read the UCSRC Register contents.
Note:
The assembly code example returns the UCSRC value in r16.
Reading the UBRRH contents is not an atomic operation and therefore it can be read as an ordi-
nary register, as long as the previous instruction did not access the register location.
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the UDR Register location. Reading the
UDR Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-bit, 6-bit, or 7-bit characters the upper unused bits will be ignored by the Transmitter and
set to zero by the Receiver.
The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data
written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When
data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the
data into the transmit Shift Register when the Shift Register is empty. Then the data will be seri-
ally transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify
write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC
and SBIS), since these also will change the state of the FIFO.
Bit
Read/Write
Initial Value
Assembly Code Example
C Code Example
USART_ReadUCSRC:
unsigned char USART_ReadUCSRC( void )
{
}
; Read UCSRC
in
in
ret
unsigned char ucsrc;
/* Read UCSRC */
ucsrc = UBRRH;
ucsrc = UCSRC;
return ucsrc;
1. See “About Code Examples” on page 7.
r16,UBRRH
r16,UCSRC
R/W
7
0
(1)
R/W
6
0
(1)
R/W
5
0
R/W
4
0
RXB[7:0]
TXB[7:0]
R/W
3
0
R/W
2
0
R/W
1
0
ATmega16(L)
R/W
0
0
UDR (Read)
UDR (Write)
163
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