ATMEGA325-16MUR Atmel, ATMEGA325-16MUR Datasheet - Page 100
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ATMEGA325-16MUR
Manufacturer Part Number
ATMEGA325-16MUR
Description
MCU AVR 32K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16AUR.pdf
(362 pages)
Specifications of ATMEGA325-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.0.1
15.0.2
15.0.3
2570M–AVR–04/11
Internal Clock Source
Prescaler Reset
External Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (
is transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 1. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
CLK_I/O
T1
/clk
/1024.
Tn
clk
T0
I/O
). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
CLK_I/O
D
LE
ExtClk
Q
). Alternatively, one of four taps from the prescaler can be used as a
Synchronization
< f
D
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T1
/clk
T
0
ATmega325/3250/645/6450
pulse for each positive (CSn2:0 = 7) or negative
D
CLK_I/O
Q
/8, f
CLK_I/O
Edge Detector
/64, f
clk
CLK_I/O
I/O
Tn_sync
(To Clock
Select Logic)
). The latch
Figure 1
/256, or
100
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