PIC18LF2455T-I/SO Microchip Technology, PIC18LF2455T-I/SO Datasheet - Page 11

• Manufacturer Part Number: PIC18LF2455T-I/SO
• Description: IC PIC MCU FLASH 12KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2455T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19. Module: EUSART
© 2009 Microchip Technology Inc.
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREG, are trans-
ferred to the TSR during the transmission of a Stop
bit. For this to occur, three things must happen in
the same instruction cycle:
• TXREG is written to
• The baud rate counter overflows (at the end of
• A Stop bit is being transmitted (shifted out of
Work around
If possible, do not use the module’s double-buffer
capability. Instead, load the TXREG register when
the TRMT bit (TXSTA<1>) is set, indicating the
TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, load TXREG immedi-
ately after TXIF is set, or wait 1 bit time after TXIF
is set. Both solutions prevent writing TXREG while
a Stop bit is transmitted. The TXIF bit is set at the
beginning of the Stop bit transmission.
If transmission is intermittent, do one of the
following:
• Wait for the TRMT bit to be set before loading
• Use a free timer resource to time the baud
Affected Silicon Revisions
the bit period)
TSR)
TXREG
period.
Set up the timer to overflow at the end of a
Stop bit, then start the timer when you load the
TXREG. Do not load the TXREG when timer
is about to overflow.
A3
X
B4
B5
B6
PIC18F2455/2550/4455/4550
B7
20. Module: EUSART
21. Module: EUSART
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after the
RCIDL bit (BAUDCON<6>) is set.
Work around
Write to TX9D only when a reception is not in
progress (RCIDL = 1). Since there is no interrupt
associated with RCIDL, it must be polled in
software to determine when TX9D can be
updated.
Affected Silicon Revisions
After the last received byte has been read from the
EUSART receive buffer (RCREG), the value is no
longer valid for subsequent read operations.
Work around
The RCREG register should only be read once for
each byte received. After each byte is received
from the EUSART, store the byte in a user
variable.
To determine when a byte is available to read from
RCREG, poll the RCIDL bit (BAUDCON<6>) for a
low-to-high transition, or use the EUSART Receive
Interrupt Flag, RCIF (PIR1<5>).
Affected Silicon Revisions
A3
A3
X
X
B4
B4
B5
B5
DS80478A-page 11
B6
B6
B7
B7