PIC18LF2221-I/SP Microchip Technology, PIC18LF2221-I/SP Datasheet - Page 225
![IC PIC MCU FLASH 2KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2221-I/SP
Manufacturer Part Number
PIC18LF2221-I/SP
Description
IC PIC MCU FLASH 2KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
6.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18LF2221-I/SP
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- PIC18F2321-IML PDF datasheet #6
- Current page: 225 of 402
- Download datasheet (7Mb)
FIGURE 19-6:
FIGURE 19-7:
TABLE 19-6:
© 2009 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing
the OERR (overrun) bit to be set.
These bits are unimplemented on 28-pin devices and read as ‘0’.
RX
BRG16
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
EUSART RECEIVE BLOCK DIAGRAM
ASYNCHRONOUS RECEPTION, TXCKP = 0 (TX NOT INVERTED)
PIC18F2221/2321/4221/4321 FAMILY
Start
bit
SPBRGH
Baud Rate Generator
x64 Baud Rate CLK
RXDTP
bit 0
RCIDL
and Control
ADIF
ADIE
ADIP
Pin Buffer
Bit 6
RX9
TX9
bit 1
SPBRG
SPEN
TMR0IE
RXDTP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
bit 7/8
Recovery
Interrupt
÷ 64
÷ 16
÷ 4
Data
TXCKP
Stop
INT0IE
CREN
SYNC
or
or
bit
TXIE
TXIP
Bit 4
TXIF
Word 1
RCREG
CREN
Start
bit
ADDEN
SENDB
bit 0
BRG16
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
RX9
Stop
MSb
RCIF
RCIE
RX9D
TMR0IF
CCP1IF
CCP1IE
CCP1IP
bit 7/8
BRGH
Word 2
RCREG
FERR
(8)
Bit 2
—
OERR
7
Stop
bit
RSR Register
RCREG Register
• • •
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
8
Start
WUE
Bit 1
bit
Data Bus
1
FERR
0
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
bit 7/8
Bit 0
DS39689F-page 225
LSb
Start
FIFO
Stop
bit
on page
Values
Reset
57
57
57
57
57
55
58
58
58
57
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