PIC16LCE625-04I/SS Microchip Technology, PIC16LCE625-04I/SS Datasheet - Page 30

• Manufacturer Part Number: PIC16LCE625-04I/SS
• Description: IC MCU CMOS 2K OTP W/EEPRM20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LCE625-04I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Other names: PIC16LCE62504I/SS

PIC16CE62X
6.1
In this section, the term “processor” refers to the portion
of the PIC16CE62X that interfaces to the EEPROM
through software manipulating the EEINTF register.
The following bus protocol is to be used with the
EEPROM data memory.
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 6-1).
6.1.1
Both data and clock lines remain HIGH.
6.1.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
6.1.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
6.1.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the processor and
is theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out fashion.
DS40182C-page 30
is not busy.
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted by the EEPROM as a START or STOP
condition.
Bus Characteristics
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
DATA VALID (D)
6.1.5
The EEPROM will generate an acknowledge after the
reception of each byte. The processor must generate
an extra clock pulse which is associated with this
acknowledge bit.
When the EEPROM acknowledges, it pulls down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-2).
Note:
ACKNOWLEDGE
Acknowledge bits are not generated if an
internal programming cycle is in progress.
1999 Microchip Technology Inc.
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