ATMEGA169PV-8MCHR Atmel, ATMEGA169PV-8MCHR Datasheet - Page 311
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ATMEGA169PV-8MCHR
Manufacturer Part Number
ATMEGA169PV-8MCHR
Description
MCU AVR 16KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA169PV-8AU.pdf
(395 pages)
Specifications of ATMEGA169PV-8MCHR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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27.8.1
27.8.2
8018P–AVR–08/10
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 27-14. Pin Mapping Serial Programming
Figure 27-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega169P, data is clocked on the rising edge of SCK.
When reading data from the ATmega169P, data is clocked on the falling edge of SCK. See
ure 27-11 on page 313
To program and verify the ATmega169P in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in
1. Power-up sequence:
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
Symbol
MOSI
MISO
SCK
XTAL1 pin.
CC
- 0.3V < AVCC < V
for timing details.
CC
and GND while RESET and SCK are set to “0”. In some sys-
MOSI
MISO
SCK
ck
ck
CC
Pins
PB2
PB3
PB1
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V
XTAL1
RESET
GND
(1)
AVCC
VCC
+1.8V - 5.5V
+1.8V - 5.5V
I/O
O
I
I
Table 27-16 on page
(2)
ck
ck
ATmega169P
>= 12 MHz
>= 12 MHz
Serial Data out
Serial Data in
Description
Serial Clock
314):
Fig-
311
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