PIC18F65K22-I/PTRSL Microchip Technology, PIC18F65K22-I/PTRSL Datasheet - Page 64

• Manufacturer Part Number: PIC18F65K22-I/PTRSL
• Description: MCU PIC 32K FLASH MEM XLP 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 2048Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
REGISTER 4-2:
DS39960B-page 64
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
TMR10MD
R/W-0
2:
3:
(1,3)
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Section 18.0 “Real-Time
Clock and Calendar (RTCC)” for the unlock sequence (Example 18-1).
Unimplemented on devices with 64 pins (PIC18F6XK22).
TMR10MD: TMR10MD Disable bit
1 = Peripheral Module Disable (PMD) is enabled and all TMR10MD clock sources are disabled
0 = PMD is disabled and TMR10MD is enabled
TMR8MD: TMR8MD Disable bit
1 = PMD is enabled and all TMR8MD clock sources are disabled
0 = PMD is disabled and TMR8MD is enabled
TMR7MD: TMR7MD Disable bit
1 = PMD is enabled and all TMR7MD clock sources are disabled
0 = PMD is disabled and TMR7MD is enabled
TMR6MD: TMR6MD Disable bit
1 = PMD is enabled and all TMR6MD clock sources are disabled
0 = PMD is disabled and TMR6MD is enabled
TMR5MD: TMR5MD Disable bit
1 = PMD is enabled and all TMR5MD clock sources are disabled
0 = PMD is disabled and TMR5MD is enabled
CMP3MD: PMD Comparator 3 Enable/Disable bit
1 = PMD is enabled for Comparator 3, disabling all of its clock sources
0 = PMD is disabled for Comparator 3
CMP2MD: PMD Comparator 3 Enable/Disable bit
1 = PMD is enabled for Comparator 2, disabling all of its clock sources
0 = PMD is disabled for Comparator 2
CMP1MD: PMD Comparator 3 Enable/Disable bit
1 = PMD is enabled for Comparator 1, disabling all of its clock sources
0 = PMD is disabled for Comparator 1
TMR8MD
R/W-0
PMD2: PERIPHERAL MODULE DISABLE REGISTER 2
W = Writable bit
‘1’ = Bit is set
TMR7MD
R/W-0
(1)
TMR6MD
(1,3)
(1)
R/W-0
Preliminary
(1,3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TMR5MD
R/W-0
CMP3MD
R/W-0
(2)
 2010 Microchip Technology Inc.
x = Bit is unknown
CMP2MD
R/W-0
CMP1MD
R/W-0
bit 0