PIC16F76T-I/SO Microchip Technology, PIC16F76T-I/SO Datasheet - Page 322
![IC MCU FLASH 8KX14 A/D 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F76T-I/SO
Manufacturer Part Number
PIC16F76T-I/SO
Description
IC MCU FLASH 8KX14 A/D 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F76T-I/SO
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC16F
No. Of I/o's
22
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 322 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.14
17.4.14.1 WCOL Status Flag
DS31017A-page 17-46
Stop Condition Timing
A stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop
sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held
low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the
SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts
down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one
T
pin is sampled high while SCL is high the P bit (SSPSTAT<4>) is set. A T
is cleared and the SSPIF bit is set
Whenever the firmware decides to take control of the bus, it will first determine if the bus is busy
by checking the S and P bits in the SSPSTAT register. If the bus is busy, then the CPU can be
interrupted (notified) when a Stop bit is detected (i.e. bus is free).
If the user writes the SSPBUF when a STOP sequence is in progress, then the WCOL bit is set
and the contents of the buffer are unchanged (the write doesn’t occur).
Figure 17-31: Stop Condition Receive or Transmit Mode
BRG
SCL
SDA
(baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA
Write to SSPCON2
Falling edge of
9th clock
Note: T
ACK
Set PEN
BRG
= one baud rate generator period.
SDA asserted low before rising edge of clock
to setup stop condition.
Preliminary
T
T
BRG
BRG
(Figure
T
SCL brought high after T
BRG
17-31).
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set
P
T
BRG
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
, followed by SDA = 1 for T
BRG
1997 Microchip Technology Inc.
BRG
later, the PEN bit
BRG
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