ATMEGA644PA-MUR Atmel, ATMEGA644PA-MUR Datasheet - Page 297
ATMEGA644PA-MUR
Manufacturer Part Number
ATMEGA644PA-MUR
Description
IC MCU AVR 64K FLASH 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PA-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8272A–AVR–01/10
Table 26-4.
Note:
Table 26-5.
Note:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Fuse High Byte
OCDEN
JTAGEN
SPIEN
WDTON
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(1)
1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See
3. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See
3. The CKOUT Fuse allow the system clock to be output on PORTB1. See
4. See
(3)
(4)
(4)
(3)
290
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
See
page 31
on page 39
Fuse High Byte
Fuse Low Byte
for details.
”WDTCSR – Watchdog Timer Control Register” on page 60
”System and Reset Characteristics” on page 335
”System Clock Prescaler” on page 40
for details.
Bit No
Bit No
for details.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Description
Divide clock by 8
Clock output
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
Description
Enable OCD
Enable JTAG
Enable Serial Program and Data
Downloading
Watchdog Timer always on
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
details)
Select Boot Size (see
details)
Select Reset Vector
for details.
Table 26-9
Table 26-9
for details.
for
for
Default Value
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
1 (unprogrammed)
Default Value
1 (unprogrammed, OCD
disabled)
0 (programmed, JTAG enabled)
0 (programmed, SPI prog.
enabled)
1 (unprogrammed)
1 (unprogrammed, EEPROM
not preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
for details.
Table 25-10 on page
”Clock Output Buffer”
(2)
(2)
(1)
(2)
(2)
(2)
(1)
(2)
Table 8-1 on
297
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