PIC24HJ16GP304-I/PT Microchip Technology, PIC24HJ16GP304-I/PT Datasheet - Page 37
![IC PIC MCU FLASH 16K 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC24HJ16GP304-I/PT
Manufacturer Part Number
PIC24HJ16GP304-I/PT
Description
IC PIC MCU FLASH 16K 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
5.PIC24HJ16GP304-IPT.pdf
(260 pages)
Specifications of PIC24HJ16GP304-I/PT
Core Size
16-Bit
Program Memory Size
16KB (5.5K x 24)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Number Of I /o
35
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
2KB
Cpu Speed
40MIPS
No. Of Timers
4
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ16GP304-I/PT
Manufacturer:
MICROCHIP
Quantity:
367
Company:
Part Number:
PIC24HJ16GP304-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
5.5
The procedure for erasing program memory (all of code
memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
0x404F and then executing the programming cycle. For
segment erase operations, the NVMCON value should
be modified suitably, according to
Figure 5-6
for Bulk Erasing program memory. This process
includes the ICSP command code, which must be
transmitted (for each instruction) Least Significant bit
first, using the PGCx and PGDx pins (see
FIGURE 5-6:
If a Segment Erase operation is required, Step 3 must
be modified with the appropriate NVMCON value as
per
The ability to individually erase various segments is a
critical component of the CodeGuard™ Security
features on dsPIC33F/PIC24H devices. An individual
code segment may be erased without affecting other
segments. In addition, the Configuration register
corresponding to the erased code segment also gets
erased. For example, the user may want to erase the
code in the General Segment without erasing
a bootloader located in the Boot Segment.
© 2010 Microchip Technology Inc.
Note:
Table
Erasing Program Memory
5-2.
illustrates the ICSP programming process
Write 0x404F to NVMCON SFR
Program memory must be erased before
writing any data to program memory.
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
BULK ERASE FLOW
Start
End
Table
5-2.
Figure
5-2).
The Secure Segment Erase command is used to erase
the Secure Segment and the FSS Configuration
register. The General Segment Erase command is
used to erase the General Segment and the FGS
Configuration register. This command is only effective
if a Boot Segment or Secure Segment has been
enabled.
Before performing any segment erase operation, the
programmer must first determine if the dsPIC33F/
PIC24H device has defined a Boot Segment or Secure
Segment, and ensure that a segment does not get
overwritten by operations on any other segment.
The BSS bit field in the FBS Configuration register can
be read to determine whether a Boot Segment has
been defined. If a Boot Segment has already been
defined (and probably already been programmed), the
user must be warned about this fact. Similarly, the SSS
bit field in the FSS Configuration register can be read
to determine whether a Secure Segment has been
defined. If a Secure Segment has already been defined
(and probably already been programmed), the user
must be warned about this fact.
A Bulk Erase operation is the recommended
mechanism to allow a user to overwrite the Boot
Segment (if one chooses to do so).
In
Security-related Configuration registers should be
programmed in the following order:
• FBS and Boot Segment
• FSS and Secure Segment
• FGS and General Segment
Note 1: The
general,
2: A Secure Segment Erase operation also
Configuration register can only be erased
using a Bulk Erase.
erases the General Segment and FGS
Configuration register. This is true even if
Secure Segment is present on a device
but not enabled.
the
Boot
segments
Segment
and
DS70152H-page 37
and
CodeGuard
FBS