DSPIC30F3014T-20E/ML Microchip Technology, DSPIC30F3014T-20E/ML Datasheet - Page 14

• Manufacturer Part Number: DSPIC30F3014T-20E/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3014T-20E/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F3014/4013
19. Module: I/O
20. Module: I
21. Module: Timer
DS80455D-page 14
If the user application enables the auto-baud
feature in the UART module, the I/O pin
multiplexed with the IC1 (Input Capture) pin cannot
be used as a digital input. However, the external
interrupt function (INT1) can be used.
Work around
None.
Affected Silicon Revisions
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are config-
ured for 10-bit addressing mode, and have the
same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
Affected Silicon Revisions
When the timer is being operated in the
asynchronous
oscillator (32.768 kHz) and the device is put into
Sleep mode, a clock switch to any other oscillator
mode before putting the device to Sleep prevents
the timer from waking the device from Sleep.
Work around
Do not clock switch to any other oscillator mode if
the timer is being used in the asynchronous mode
using the secondary oscillator (32.768 kHz).
Affected Silicon Revisions
A1
A1
A1
X
X
X
2
C devices, the addresses as well as bits
A2
A2
A2
X
X
X
2
C
mode
2
C devices on the bus, one of
using
the
secondary
22. Module: PLL
23. Module: PSV Operations
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
Work around
The user application must include an oscillator
failure trap service routine. In the trap service
routine, first inspect the status of the Clock Failure
Status bit (OSCCON<3>). If this bit is clear, return
from the trap service routine immediately and
continue program execution.
Affected Silicon Revisions
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
A1
A1
X
mode) with pre/post-decrement
X
A2
A2
X
X
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