ATMEGA645A-MUR Atmel, ATMEGA645A-MUR Datasheet - Page 159
![IC MCU AVR 64K FLASH 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA645A-MUR
Manufacturer Part Number
ATMEGA645A-MUR
Description
IC MCU AVR 64K FLASH 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA645A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA645A-MUR
Manufacturer:
TI
Quantity:
6 700
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18. SPI – Serial Peripheral Interface
18.1
18.2
8285B–AVR–03/11
Features
Overview
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
•
•
•
•
•
•
•
•
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P and peripheral
devices or between several AVR devices.
The PRSPI bit in
enable SPI module.
Figure 18-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
”PRR – Power Reduction Register” on page 45
Figure 1-1 on page
(1)
2, and
Table 13-3 on page 76
for SPI pin placement.
must be written to zero to
Figure
18-2. The sys-
159
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