PIC18F85J90-I/PT Microchip Technology, PIC18F85J90-I/PT Datasheet - Page 2

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PIC18F85J90-I/PT

Manufacturer Part Number
PIC18F85J90-I/PT
Description
IC PIC MCU FLASH 16KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F85J90-I/PT

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
67
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm Channels
2
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
67
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163030
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F85J90-I/PT
Manufacturer:
MICROCHIP
Quantity:
3 000
Part Number:
PIC18F85J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F85J90 FAMILY
TABLE 2:
DS80488B-page 2
Reset
MSSP
MSSP
EUSART
Timer1/3 Counter
Timer1/3 Prescale
EUSART
Note 1:
Module
BOR
I
Master
I
Enable/
Disable
Synchronous
mode
Only those issues indicated in the last column apply to the current silicon revision.
2
2
C™
C Master
Feature
SILICON ISSUE SUMMARY
Number
Item
1.
2.
3.
4.
5.
6.
7.
BOR and POR may occur the same time
If the SSPBUF register is not read within
a window after the SSPIF interrupt, the
module may not receive the correct data.
The Clock may get Narrow if the Slave
performs a clock stretch.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 TCY
delay.
Timer1/3 in internal counter mode will
not increment in the instruction count
where the Timer is disabled.
Timer1/3 Prescale will take additional
count to Switch when prescaler value is
changed.
The TRMT bit may not indicate when the
TSR register is empty.
Issue Summary
A3
X
X
X
X
X
X
X
 2010 Microchip Technology Inc.
Affected Revisions
A4
X
X
X
X
X
X
X
A5
X
X
X
X
X
X
X
A6
X
X
X
X
X
X
X
(1)

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