DSPIC30F2011-30I/ML Microchip Technology, DSPIC30F2011-30I/ML Datasheet - Page 127

• Manufacturer Part Number: DSPIC30F2011-30I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2011-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DAF30-4 - DEVICE ATP FOR ICE4000
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F201130IML

17.3
The PIC18F1220/1320 differentiates between various
kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 17-2:
17.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally
characteristics must meet specified starting voltage
and rise rate requirements. The POR pulse will reset a
POR timer and place the device in the Reset state. The
POR also selects the device clock source identified by
the oscillator configuration fuses.
© 2008 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lockup (TRAPR)
Reset caused by illegal opcode or by using an
uninitialized W register as an address pointer
(IOPUWR)
MCLR
V
DD
Reset
DD
Instruction
POR: POWER-ON RESET
RESET
rise is detected. The Reset pulse will occur
1.85V.
Trap Conflict
Illegal Opcode/
Uninitialized W Register
Brown-out
V
Sleep or Idle
Module
DD
Detect
WDT
Reset
The
RESET SYSTEM BLOCK DIAGRAM
Rise
device
BOREN
Glitch Filter
Digital
POR
supply
dsPIC30F2011/2012/3012/3013
POR
) which is
BOR
voltage
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 17-5. These bits
are used in software to determine the nature of the
Reset.
A block diagram of the On-Chip Reset Circuit is shown
in Figure 17-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected
power-up time-out (T
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
delay is at device power-up, T
these delays have expired, SYSRST will be negated on
the next leading edge of the Q1 clock and the PC will
jump to the Reset vector.
The timing for the SYSRST signal is shown in
Figure 17-3 through Figure 17-5.
S
PWRT
R
) is applied. The T
Q
POR
DS70139F-page 127
+ T
POR
SYSRST
PWRT
, which is
. When
PWRT