PIC16C63A-20E/SS Microchip Technology, PIC16C63A-20E/SS Datasheet - Page 60

• Manufacturer Part Number: PIC16C63A-20E/SS
• Description: IC MCU OTP 4KX14 PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63A-20E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

PIC16C63A/65B/73B/74B
10.3
The SSP module in I
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementation of the master func-
tions. The SSP module implements the standard mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer, the RC3/SCK/SCL
pin, which is the clock (SCL), and the RC4/SDI/SDA
pin, which is the data (SDA). The user must configure
these pins as inputs or outputs through the
TRISC<4:3> bits. External pull-up resistors for the SCL
and SDA pins must be provided in the application cir-
cuit for proper operation of the I
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 10-5:
The SSP module has five registers for I
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - not directly accessible
• SSP Address Register (SSPADD)
DS30605C-page 60
RC3/SCK/SCL
RC4/SDI/
SDA
SSP I
2
Read
C Operation
Clock
Shift
2
C mode fully implements all slave
MSb
SSP BLOCK DIAGRAM
(I
2
STOP bit Detect
C MODE)
Match Detect
SSPADD reg
SSPBUF reg
START and
SSPSR reg
2
C module.
LSb
Write
(SSPSTAT reg)
2
Internal
Data Bus
C operation.
Addr Match
Set, Reset
S, P bits
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
Additional information on SSP I
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
10.3.1
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally generates the acknowledge (ACK) pulse, and
then loads the SSPBUF register with the received
value currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have minimum high and low
times for proper operation. The high and low times of
the I
SSP module, is shown in timing parameter #100 and
parameter #101.
STOP bit interrupts enabled to support firmware
Master mode
STOP bit interrupts enabled to support firmware
Master mode
support firmware Master mode, Slave is idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with START and
C Slave mode (10-bit address), with START and
C START and STOP bit interrupts enabled to
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
2
C specification, as well as the requirement of the
SLAVE MODE
2
C mode with the SSPEN bit set,
2
C modes to be selected:
2000 Microchip Technology Inc.
2
C operation can be
2
C opera-