ATMEGA165A-AU Atmel, ATMEGA165A-AU Datasheet
ATMEGA165A-AU
Specifications of ATMEGA165A-AU
Available stocks
Related parts for ATMEGA165A-AU
ATMEGA165A-AU Summary of contents
Page 1
... EEPROM • 512Bytes (ATmega165A/ATmega165PA) • 1Kbytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 2Kbytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – Internal SRAM • 1KBytes (ATmega165A/ATmega165PA) • 2KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 4KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – Optional Boot Code Section with Independent Lock Bits • ...
Page 2
... Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol- dered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 2 INDEX CORNER PA3 ...
Page 3
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 1.2 Pinout - 100A (TQFP) Figure 1-2. Pinout ATmega3250A/ATmega3250PA/ATmega6450A/ATmega6450P 1 DNC 2 (RXD/PCINT0) PE0 3 (TXD/PCINT1) PE1 4 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 5 6 (USCK/SCL/PCINT4) PE4 7 (DI/SDA/PCINT5) PE5 8 (DO/PCINT6) PE6 9 (CLKO/PCINT7) PE7 VCC 10 11 GND DNC 12 13 (PCINT24) PJ0 14 (PCINT25) PJ1 15 DNC 16 DNC DNC 17 18 DNC ...
Page 4
... Overview The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a low-power CMOS 8-bit microcon- troller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, this microcontroller achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. ...
Page 5
... Atmel devise is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P AVR is sup- ported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
Page 6
... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on nate Functions of Port B” on page ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 6 ...
Page 7
... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on nate Functions of Port E” on page 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter ...
Page 8
... Port G also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on 84. 2.3.10 Port H (PH7:PH0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability ...
Page 9
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...
Page 10
... The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 10 Block Diagram of the AVR Architecture ...
Page 11
... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 12
... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 ...
Page 13
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 6.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • ...
Page 14
... The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 14 The X-, Y-, and Z-registers 15 ...
Page 15
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 6.6.1 SPH and SPL – Stack Pointer Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 6.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. ...
Page 16
... When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 16 for details. ”Interrupts” on page 55 ” ...
Page 17
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Assembly Code Example in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example ...
Page 18
... AVR Memories This section describes the different memories in the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P fea- tures an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
Page 19
... SRAM Data Memory Figure 7-2 on page 20 The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
Page 20
... Figure 7-2. 7.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 20. Figure 7-3. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 20 Data Memory Data Memory X 8 0x0000 - 0x001F 32 Registers 0x0020 - 0x005F 64 I/O Registers 0x0060 - 0x00FF 160 Ext I/O Reg ...
Page 21
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 7.3 EEPROM Data Memory The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. This section describes the access between the EEPROM and the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 22
... Symbol EEPROM write (from CPU) Note: 1. 3.3 applies to ATmega165A/ATmega165PA The following code examples show one assembly and one C function for writing to the EEPROM. To avoid that interrupts will occur during execution of these functions, the examples assume that interrupts are controlled (e.g. by disabling interrupts globally). The examples also assume that no Flash Boot Loader is present in the software ...
Page 23
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ...
Page 24
... EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 24 r16,EEDR ; ...
Page 25
... When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 26
... Register Description 7.6.1 EEARH and EEARL – EEPROM Address Register ATmega165A/ATmega165PA Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:9 – Reserved These bits are reserved and will always read as zero. • Bits 8:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – ...
Page 27
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. ...
Page 28
... GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 MSB R/W R/W R/W R LSB GPIOR0 R/W R/W R/W R 8285B–AVR–03/11 ...
Page 29
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 on page 29 of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ” ...
Page 30
... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in 2. The frequency of the Watchdog Oscillator is voltage dependent as shown in teristics” on page Table 8-2. Typ Time-out (V ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 30 ASY (1) Device Clocking Options Select 332. ...
Page 31
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 8.3 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel programmer ...
Page 32
... This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in 8-6. Table 8-6. CKSEL0 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 32 Table 8-5. For ceramic resonators, the capacitor values given by Crystal Oscillator Connections C2 C1 Crystal Oscillator Operating Modes Frequency Range (MHz) 0 ...
Page 33
... The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P oscillator is opti- mized for very low power consumption, and thus when selecting crystals, see maximum ESR recommendations on 9pF and 6.5pF crystals. ...
Page 34
... Table 8-11. CKSEL3... 0 (1) 0110 0111 Note: 1. This option should only be used if frequency stability at start-up is not important for the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 34 Maximum ESR Recommendation for 32.768kHz Watch Crystal ATmega325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Crystal CL (pF) 6.5 9.0 12.5 32kHz Osc. Type Cap (Xtal1/Tosc1) System Osc. ...
Page 35
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 8.7 External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 8-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 8-3. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 8-13 ...
Page 36
... CKOUT Fuse is programmed. 8.10 System Clock Prescaler The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P system clock can be divided by setting the be used to decrease the system clock frequency and power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 37
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 8.11 Register Description 8.11.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is ...
Page 38
... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 8-14. CLKPS3 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 38 Clock Prescaler Select CLKPS2 CLKPS1 ...
Page 39
... The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 9.2 Sleep Modes Figure 8-1 on page 29 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P, and their distribu- tion. The figure is helpful in selecting an appropriate sleep mode. sleep modes and their wake up sources and BOD disable ability Note: Table 9-1. ...
Page 40
... Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to for details. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 40 61. Writing this bit to one turns off the BOD in relevant sleep 61. ...
Page 41
... When the ADC is turned off and on again, the next 8285B–AVR–03/11 ”Clock Sources” on page ”PRR – Power Reduction Register” on page ”ATmega165A: Supply Current of I/O modules” on page 337 30. 45, pro- for exam- ...
Page 42
... For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to Input Disable Register 0” on page 231 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 42 ”AC - Analog Comparator” on page 210 for details on the start-up time. ”Watchdog Timer” on page 50 for details on how to configure the Watchdog Timer ...
Page 43
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 9.10.7 JTAG Interface and On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • ...
Page 44
... The BODS bit must be written to logic one in order to turn off BOD during sleep, see on page BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 – ...
Page 45
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. • Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description ...
Page 46
... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in 10.2 Reset Sources The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
Page 47
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 10-1. Reset Logic BODLEVEL [2..0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the start-up Reset well as to detect a failure in supply voltage. ...
Page 48
... Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V delay counter starts the MCU after the Time-out period – t Figure 10-4. External Reset During Operation ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 48 V POT ...
Page 49
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 10.2.3 Brown-out Detection ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P has an On-chip Brown-out Detection (BOD) circuit for monitoring the fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted ...
Page 50
... Internal Voltage Reference ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P features an inter- nal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...
Page 51
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 10-7. Watchdog Timer 10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 10.4.1.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction ...
Page 52
... WDTCR, r16 ret C Code Example void WDT_off(void Reset WDT */ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } Note: 1. See ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 52 (1) r16, WDTCR (1) ”About Code Examples” on page 9. 8285B–AVR–03/11 ...
Page 53
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 10.5 Register Description 10.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET ...
Page 54
... The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 54 See ”Timed Sequences for Changing the Configuration of the Watchdog Table 10-2 ...
Page 55
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 11. Interrupts ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P. For a general explanation of the AVR interrupt handling, refer to 11.1 Interrupt Vectors Table 11-1. Vector No Notes: 8285B–AVR–03/11 Reset and Interrupt Vectors Program (2) Address Source (1) 0x0000 RESET 0x0002 INT0 0x0004 PCINT0 0x0006 PCINT1 0x0008 TIMER2 COMP 0x000A TIMER2 OVF ...
Page 56
... Boot section or vice versa. Table 11-2. BOOTRST Note: 1. The Boot Reset Address is shown in The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega165A/165PA is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E ...
Page 57
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 0x0031 0x0032 0x0033 ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ...
Page 58
... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 58 RESET: ldi r16,high(RAMEND) ...
Page 59
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 ; .org 0x3802/0x7802 0x3804/0x7804 0x3806/0x7806 ... 0x1C2C When the BOOTRST Fuse is programmed and the Boot section size set to 4K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code ...
Page 60
... C Code Example void Move_interrupts(void) { uchar temp; /* Get MCUCR*/ temp = MCUCR; /* Enable change of Interrupt Vectors */ MCUCR = temp | (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = temp | (1<<IVSEL); } ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 60 61. ”Boot Loader Support – Read-While- for details on Boot Lock bits. 8285B–AVR–03/11 ...
Page 61
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 11.3 Register Description 11.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Note: • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash ...
Page 62
... PCINT30:16 are only present in ATmega3250A/3250PA/6450A/6450P. Only PCINT15:0 are 12.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 62 ”EICRA – External Interrupt Control Register A” on page 29. present in ATmega165A/165PA; ATmega325A/325PA and ATmega645A/645P. See figurations” on page 2 and ”Register Description” on page 64 (2) (1) (1) , PCMSK2 , PCMSK1, and PCMSK0 Reg- ” ...
Page 63
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 12-1. Pin Change Interrupt 8285B–AVR–03/11 pin_lat PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF pcint_in_(0) 0 pcint_syn pcint_setflag x clk PCIF 63 ...
Page 64
... The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request (1) (1) PCIE3 PCIE2 PCIE1 PCIE0 R R R/W R ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be written to zero. ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be written to zero – – ISC01 ISC00 EICRA R R R/W R – ...
Page 65
... PCIF3 PCIF2 PCIF1 R/W R/W R This bit is a reserved bit in ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be written to zero. 1. This bit is a reserved bit in ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P and should always be written to zero PCIF0 – – – R INTF0 ...
Page 66
... Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 66 ( ...
Page 67
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 12.2.7 PCMSK0 – Pin Change Mask Register 0 Bit (0x6B) Read/Write Initial Value • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin ...
Page 68
... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 68 and Ground as indicated in CC for a complete list of parameters. If exceeding the pin ...
Page 69
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 13-2. General Digital I/O Note: 13.2.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Description” ...
Page 70
... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 70 summarizes the control signals for the pin value. Port Pin Configurations ...
Page 71
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “ ...
Page 72
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 72 (1) r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1< ...
Page 73
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 13.2.6 Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode) ...
Page 74
... Pxn, PORT TOGGLE OVERRIDE ENABLE Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk Table 13-2 on page 75 indexes from signals are generated internally in the modules having the alternate function. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 74 (1) PUOExn PUOVxn 1 ...
Page 75
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 8285B– ...
Page 76
... Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function. PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt source. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 76 Port B Pins Alternate Functions Alternate Functions OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt15) ...
Page 77
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 • MISO/PCINT11 – Port B, Bit 3 MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced input, the pull-up can still be controlled by the PORTB3 bit ...
Page 78
... PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 78 Overriding Signals for Alternate Functions in PB7:PB4 PB7/OC2A/ PB6/OC1B/ PCINT15 PCINT14 OC2A ENABLE OC1B ENABLE OC2A OC1B – – PCINT15 • PCIE1 PCINT14 • ...
Page 79
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 13.3.2 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-6. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • INT0 – Port D, Bit 1 INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the MCU. • ...
Page 80
... AIN1/PCINT3 – Port E, Bit 3 AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt source. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 80 Port E Pins Alternate Functions Alternate Function ...
Page 81
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART oper- ates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator ...
Page 82
... TDI, ADC7 – Port F, Bit 7 ADC7, Analog to Digital Converter, Channel 7 TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg- ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 82 PE3/AIN1/ PE2/XCK/AIN0/ ...
Page 83
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • ...
Page 84
... RESET – Port G, Bit 5 RESET: External Reset input. When the RSTDISBL Fuse is programmed (‘0’), PG5 will function as input with pull-up always on. • T0 – Port G, Bit 4 T0, Timer/Counter0 Counter Source. • T1 – Port G, Bit 3 T1, Timer/Counter1 Counter Source. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 84 PF3/ADC3 PF2/ADC2 ...
Page 85
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 13-14 shown in Table 13-15. Overriding Signals for Alternate Functions in PG4:PG3 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.6 Alternate Functions of Port H Port H is only present in ATmega3250A/3250PA/6450A/6450P. The alternate pin configuration is as follows: Table 13-16. Port H Pins Alternate Functions ...
Page 86
... Table 13-17 shown in Table 13-17. Overriding Signals for Alternate Functions in PH7:PH4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 86 and Table 13-18 relates the alternate functions of Port H to the overriding signals Figure 13-5 on page 74. PH7/PCINT23 PH6/PCINT22 ...
Page 87
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 13-18. Overriding Signals for Alternate Functions in PH3:PH0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.7 Alternate Functions of Port J Port J is only present in ATmega3250A/3250PA/6450A/6450P. The alternate pin configuration is as follows: Table 13-19. Port J Pins Alternate Functions ...
Page 88
... Table 13-20 shown in Table 13-20. Overriding Signals for Alternate Functions in PJ7:PJ4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 88 and Table 13-21 relates the alternate functions of Port J to the overriding signals Figure 13-5 on page 74. PJ7 PJ6/PCINT30 ...
Page 89
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 13-21. Overriding Signals for Alternate Functions in PJ3:PJ0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8285B–AVR–03/11 PJ3/PCINT27 PJ2/PCINT26 – – PCINT27 • PCIE0 PCINT26 • PCIE0 0 0 – – – – PJ1/PCINT25 PJ0/PCINT24 ...
Page 90
... PORTB – Port B Data Register Bit 0x05 (0x25) Read/Write Initial Value 13.4.6 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 13.4.7 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 JTD BODS BODSE PUD R R for more details about this feature ...
Page 91
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 13.4.8 PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.4.10 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value 13.4.11 PORTD – Port D Data Register ...
Page 92
... Bit 0x13 (0x33) Read/Write Initial Value 13.4.22 PING – Port G Input Pins Address Bit 0x12 (0x32) Read/Write Initial Value 13.4.23 PORTH – Port H Data Register Bit (0xDA) Read/Write Initial Value ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 PINE7 PINE6 PINE5 PINE4 R/W R/W R/W R/W N/A N/A ...
Page 93
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 13.4.24 DDRH – Port H Data Direction Register Bit (0xD9) Read/Write Initial Value 13.4.25 PINH – Port H Input Pins Address Bit (0xD8) Read/Write Initial Value 13.4.26 PORTJ – Port J Data Register Bit (0xDD) Read/Write Initial Value 13.4.27 DDRJ – Port J Data Direction Register ...
Page 94
... Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare unit number, in this case unit A. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 94 Figure 14-1. For the actual placement of I/O pins, refer to 2 ...
Page 95
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 The definitions in Table 14-1. BOTTOM MAX TOP 14.2.2 Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter- rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg- ister (TIMSK0) ...
Page 96
... WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig- nals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 14-3 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 96 Increment or decrement TCNT0 by 1. Select between increment and decrement. ...
Page 97
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 14-3. Output Compare Unit, Block Diagram The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence ...
Page 98
... The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0A1 tells the Waveform Generator that no action on the OC0A Register performed on the next compare match. For compare output actions in the non-PWM modes refer page ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 98 COMnx1 Waveform COMnx0 ...
Page 99
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits. 14.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits ...
Page 100
... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 100 ...
Page 101
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 14-6. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. ...
Page 102
... The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 102 1 2 ...
Page 103
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in there is no Compare Match. The point of this transition is to guarantee symmetry around BOT- TOM. There are two cases that give a transition without Compare Match. • ...
Page 104
... Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk I/O clk Tn (clk /8) I/O TCNTn (CTC) OCRnx OCFnx ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 104 OCRnx - 1 OCRnx shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. caler (f /8) clk_I/O TOP - 1 TOP clk_I/O OCRnx + 1 ...
Page 105
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 14.9 Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written when operating in PWM mode ...
Page 106
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 106 Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits ...
Page 107
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 14-6. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 14.9.2 TCNT0 – Timer/Counter Register Bit 0x26 (0x46) Read/Write ...
Page 108
... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 108 – ...
Page 109
... TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the 130 ...
Page 110
... The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). put Compare Units” on page Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 110 Count Clear ...
Page 111
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICP1 the Analog Comparator pins - Analog Comparator” on page Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register set of fixed values ...
Page 112
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 112 (1) (1) See ” ...
Page 113
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned int TIM16_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ...
Page 114
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 114 (1) (1) See ” ...
Page 115
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con- taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits ...
Page 116
... TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 116 DATA BUS TEMP (8-bit) ...
Page 117
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 For more information on how to access the 16-bit registers refer to on page 15.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit ...
Page 118
... The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is dis- ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 118 (See ”Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “n” in the register and ...
Page 119
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP) ...
Page 120
... PWM refer to page 131. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 120 Waveform D Generator OCnx ...
Page 121
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 15.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do ...
Page 122
... High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 122 1 2 ...
Page 123
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15) ...
Page 124
... In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 124 Table on page f ...
Page 125
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation ...
Page 126
... The diagram includes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 126 f = OCnxPCPWM 15-9) ...
Page 127
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP ...
Page 128
... PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 128 Figure 15-10 I/O ...
Page 129
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 15-12. Timer/Counter Timing Diagram, no Prescaling (PC and PFC PWM) Figure 15-13 Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 8285B–AVR–03/11 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used ...
Page 130
... WGM1[3:0] bits setting... WGM1[3:0] bits are set to a Normal or a CTC mode (non-PWM). Table 15-2. COM1A1/COM1B1 Table 15-3 PWM mode. Table 15-3. COM1A1/COM1B1 Note special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 130 COM1A1 COM1A0 COM1B1 COM1B0 ...
Page 131
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 15-4 correct or the phase and frequency correct, PWM mode. Table 15-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM1[1:0]: Waveform Generation Mode Combined with the WGM1[3:2] bits found in the TCCR1B Register, these bits control the count- ing sequence of the counter, the source for maximum (TOP) counter value, and what type of ...
Page 132
... When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 132 (1) WGM10 ...
Page 133
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 When the ICR1 is used as TOP value (see description of the WGM1[3:0] bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • ...
Page 134
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 134 7 6 ...
Page 135
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 15.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value ...
Page 136
... The setting of this flag is dependent of the WGM1[3:0] bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Flag behavior when using another WGM1[3:0] bits setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 136 – ...
Page 137
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 16. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1 Prescaler Reset The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’ ...
Page 138
... An external clock source can not be prescaled. Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1 clk I/O PSR10 T0 T1 Note: 1. The synchronization logic on the input pins ( ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 138 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O Clear Synchronization Synchronization ...
Page 139
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 16.4 Register Description 16.4.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres- caler reset signals asserted ...
Page 140
... Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 140 ”Pin Configurations” on page ”Register Description” on page ...
Page 141
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac- tive when no clock source is selected ...
Page 142
... Output mode (COM2A[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page Figure 17-3 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 142 Increment or decrement TCNT2 by 1. Selects between increment and decrement. ...
Page 143
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Figure 17-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare Register to either top or bottom of the counting sequence ...
Page 144
... Note that some COM2A[1:0] bits settings are reserved for certain modes of operation. 17.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A[1:0] bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A[1: tells the Waveform Generator that no action ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 144 Waveform D Generator OCnx ...
Page 145
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 on the OC2A Register performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 17-4 on page A change of the COM2A[1:0] bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2A strobe bits ...
Page 146
... In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 146 when OCR2A is set to zero (0x00) ...
Page 147
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 17-6. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value ...
Page 148
... OCR2A and TCNT2 when the counter increments, and setting (or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the coun- ter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 148 1 2 ...
Page 149
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode ...
Page 150
... OCRnx OCFnx Figure 17-11 Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 150 I/O Tn /8) I/O MAX - 1 MAX shows the setting of OCF2A in all modes except CTC mode. I/O Tn /8) ...
Page 151
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 17.9 Asynchronous operation of the Timer/Counter 17.9.1 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: a ...
Page 152
... The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 152 8285B–AVR–03/11 ...
Page 153
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 17.10 Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 TOSC1 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2 ...
Page 154
... However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM2[1:0] bit setting. bits are set to a normal or CTC mode (non-PWM). ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 154 ...
Page 155
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 17-3. COM2A1 Table 17-4 PWM mode. Table 17-4. COM2A1 Note: Table 17-5 correct PWM mode. Table 17-5. COM2A1 Note: 8285B–AVR–03/11 Compare Output Mode, non-PWM Mode COM2A0 Description 0 0 Normal port operation, OC2A disconnected Toggle OC2A on compare match. ...
Page 156
... Read/Write Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2A pin. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 156 Clock Select Bit Description CS21 CS20 Description ...
Page 157
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 17.11.4 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Coun- ter 2 Interrupt Flag Register – ...
Page 158
... If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 139 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 158 7 6 ...
Page 159
... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P and peripheral devices or between several AVR devices. The PRSPI bit in enable SPI module. Figure 18-1. SPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator ...
Page 160
... Low period: longer than 2 CPU clock cycles High period: longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 160 Table 18-1. For more details on automatic port overrides, refer to 74. ...
Page 161
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 18-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins ...
Page 162
... SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: 1. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 162 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPDR,r16 (1) ; ”About Code Examples” on page 9 ...
Page 163
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8285B–AVR–03/11 (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) ...
Page 164
... Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 164 8285B–AVR–03/11 ...
Page 165
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 18.4 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 18-3 and nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 18-3 Table 18-2 ...
Page 166
... SCK. Refer to functionality is summarized below: Table 18-4. • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 166 ...
Page 167
... Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is also used for program memory and EEPROM downloading or uploading. See ming and verification. 8285B–AVR–03/11 Relationship Between SCK and the Oscillator Frequency ...
Page 168
... Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 168 7 6 ...
Page 169
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19. USART 19.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with Data Bits and Stop Bits • ...
Page 170
... The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 170 (1) UBRR[H:L] ...
Page 171
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.2.1 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • ...
Page 172
... Double Speed Operation (U2Xn) The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 172 Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). ...
Page 173
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Setting this bit will reduce the divisor of the baud rate divider from effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used ...
Page 174
... The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 174 illustrates the possible combinations of the frame formats. Bits inside ...
Page 175
... ATmega165A/165PA/325A/325PA/3250A/3250PA used, the parity bit is located between the last data bit and first stop bit of a serial frame. 19.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage ...
Page 176
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 176 (1) UBRR0H, r17 UBRR0L, r16 r16, (1< ...
Page 177
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions ...
Page 178
... These transmit functions are written to be general functions. They can be optimized if the con- 2. The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 178 (1)(2) UCSR0B,TXB80 UCSR0B,TXB80 ...
Page 179
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.6.3 Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data ...
Page 180
... Get and return received data from buffer */ return UDR0; } Note: 1. The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the value. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 180 (1) r16, UDR0 (1) ; See ”About Code Examples” on page 9. ...
Page 181
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.7.2 Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Sta- tus Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change ...
Page 182
... The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 182 (1) r18, UCSR0A r17, UCSR0B ...
Page 183
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i ...
Page 184
... The following code example shows how to flush the receive buffer. Assembly Code Example USART_Flush: sbis UCSR0A, RXC0 ret in rjmp USART_Flush C Code Example void USART_Flush( void ) { unsigned char dummy; while ( UCSR0A & (1<<RXC0) ) dummy = UDR0; } Note: 1. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 184 (1) r16, UDR0 (1) See ”About Code Examples” on page 9. 8285B–AVR–03/11 ...
Page 185
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam- ples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver ...
Page 186
... Receiver does not have a similar (see Table 19-2 on page frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 186 ...
Page 187
... ATmega165A/165PA/325A/325PA/3250A/3250PA slow Table 19-2 that Normal Speed mode has higher toleration of baud rate variations. Table 19-2. # (Data+Parity Bit) Table 19-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. ...
Page 188
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 188 8285B–AVR–03/11 ...
Page 189
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.10 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRRn settings in values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table ...
Page 190
... Max. 230.4 kbps 460.8 kbps ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 190 f = 4.0000MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2. ...
Page 191
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 Table 19-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 -0.8% 68 19.2k 25 0.2% 51 28.8k 16 2.1% 34 38. ...
Page 192
... Max. 1 Mbps 2 Mbps 1. UBRRn = 0, Error = 0.0% ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 192 f = 18.4320MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 479 0.0% 959 -0.1% 239 0.0% 479 0.2% 119 0.0% 239 -0.1% 79 0.0% 159 ...
Page 193
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.11 Register Description 19.11.1 UDRn – USART I/O Data Register Bit (0xC6) Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg- ister (TXB) will be the destination for data written to the UDRn Register location ...
Page 194
... Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 194 ”Multi-processor Communication Mode” on page ...
Page 195
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. ...
Page 196
... This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 19-12. UCPOLn Bit Settings UCPOLn 0 1 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 196 UPM Bits Settings UPMn0 Parity Mode 0 0 ...
Page 197
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 19.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers Bit (0xC5) (0xC4) Read/Write Initial Value • Bit 15:12 – Reserved These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. ...
Page 198
... Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 198 Figure 21-1 on page ”Pin Configurations” on page ” ...
Page 199
... ATmega165A/165PA/325A/325PA/3250A/3250PA/6 The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete ...
Page 200
... Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. 20.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: sts ldi sts ldi SPITransfer_loop: sts lds ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645 200 ( Reference ) MSB MSB 6 5 ...