ATMEGA329P-20ANR Atmel, ATMEGA329P-20ANR Datasheet - Page 205
![MCU AVR 32K FLASH 20MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA329P-20ANR
Manufacturer Part Number
ATMEGA329P-20ANR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA329P-20ANR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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20.3.5
20.3.6
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
8021G–AVR–03/11
Alternative USI Usage
Start Condition Detector
Clock speed considerations.
Half-duplex Asynchronous Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge Triggered External Interrupt
Software Interrupt
The start condition detector is shown in
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in Two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the processor
from the Power-down sleep mode. However, the protocol used might have restrictions on the
SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by
the CKSEL Fuses (see
into the consideration. Refer to the USISIF bit description on page 206 for further details.
Maximum frequency for SCL and SCK is f
receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-
trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the
actual data rate in two-wire mode.
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact
and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
”Clock Systems and their Distribution” on page
Figure 20-6
CK
/4. This is also the maximum data transmit and
The SDA line is delayed (in the range of 50
ATmega329P/3290P
27) must also be taken
205
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