PIC16F876AT-I/SO Microchip Technology, PIC16F876AT-I/SO Datasheet - Page 331
PIC16F876AT-I/SO
Manufacturer Part Number
PIC16F876AT-I/SO
Description
IC MCU CMOS 20MHZ 8K FLSH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F876AT-I/SO
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC16F
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 331 of 688
- Download datasheet (3Mb)
17.4.18.3 Bus Collision During a STOP Condition
1997 Microchip Technology Inc.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
P
Bus collision occurs during a STOP condition if:
a)
b)
The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is
allow to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded
with SSPADD<6:0> and counts down to 0. After the BRG times out SDA is sampled. If SDA is
sampled low, a bus collision has occurred. This is due to another master attempting to drive a
data '0'
collision occurs. This is another case of another master attempting to drive a data '0'
(Figure
Figure 17-40: Bus Collision During a STOP Condition (Case 1)
Figure 17-41: Bus Collision During a STOP Condition (Case 2)
After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low
after the BRG has timed out.
After the SCL pin is de-asserted, SCL is sampled low before SDA goes high.
(Figure
17-41).
Assert SDA
T
SDA asserted low
BRG
17-40). If the SCL pin is sampled low before SDA is allowed to float high, a bus
T
BRG
Preliminary
T
BRG
T
BRG
Section 17. MSSP
SCL goes low before SDA goes high
Set BCLIF
T
BRG
T
BRG
DS31017A-page 17-55
'0'
'0'
SDA sampled
low after T
Set BCLIF
'0'
'0'
BRG
,
17
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