DSPIC30F2020-20E/SP Microchip Technology, DSPIC30F2020-20E/SP Datasheet - Page 40
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DSPIC30F2020-20E/SP
Manufacturer Part Number
DSPIC30F2020-20E/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-20E/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
15MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 5.5V
Package
28SPDIP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
11.6
The procedure for erasing program memory (all code
memory and data memory) in low-voltage systems
(with V
different than the procedure for erasing program
memory in normal-voltage systems. Instead of using a
Bulk Erase operation, each region of memory must be
individually erased by row. Namely, all of the code
memory, executive memory and data memory must be
erased one row at a time. This procedure is detailed in
Table
TABLE 11-5:
DS70102K-page 40
Step 1: Exit the Reset vector.
0000
0000
0000
Step 2: Initialize NVMADR and NVMADRU to erase code memory and initialize W7 for row address updates.
0000
0000
0000
0000
Step 3: Set NVMCON to erase 1 row of code memory.
0000
0000
Step 4: Unlock the NVMCON to erase 1 row of code memory.
0000
0000
0000
0000
Step 5: Initiate the erase cycle.
0000
0000
0000
—
0000
0000
0000
0000
0000
Command
(Binary)
11-5.
DD
Erasing Program Memory in
Low-Voltage Systems
between 2.5 volts and 4.5 volts) is quite
040100
040100
000000
EB0300
883B16
883B26
200407
24071A
883B0A
200558
883B38
200AA9
883B39
A8E761
000000
000000
—
000000
000000
A9E761
000000
000000
(Hexadecimal)
SERIAL INSTRUCTION EXECUTION FOR ERASING PROGRAM MEMORY
(EITHER IN LOW-VOLTAGE OR NORMAL-VOLTAGE SYSTEMS)
Data
GOTO 0x100
GOTO 0x100
NOP
CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
BSET NVMCON, #WR
NOP
NOP
Externally time ‘P13a’ ms (see
Timing
NOP
NOP
BCLR NVMCON, #WR
NOP
NOP
Requirements”)
W6
W6, NVMADR
W6, NVMADRU
#0x40, W7
#0x4071, W10
W10, NVMCON
#0x55, W8
W8, NVMKEY
#0xAA, W9
W9, NVMKEY
Due to security restrictions, the FBS, FSS and FGS
register cannot be erased in low-voltage systems.
Once any bits in the FGS register are programmed to
‘0’, they can only be set back to ‘1’ by performing a Bulk
Erase in a normal-voltage system. Alternatively, a Seg-
ment Erase operation can be performed instead of a
Bulk Erase.
Normal-voltage systems can also be used to erase
program memory as shown in
since this method is more time-consuming and does
not clear the code-protect bits, it is not recommended.
Note:
Description
Section 13.0 “AC/DC Characteristics and
Program memory must be erased before
writing any data to program memory.
© 2010 Microchip Technology Inc.
Table
11-5. However,