DSPIC30F4012T-20E/SO Microchip Technology, DSPIC30F4012T-20E/SO Datasheet - Page 164

• Manufacturer Part Number: DSPIC30F4012T-20E/SO
• Description: IC DSPIC MCU/DSP 48K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012T-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 21-7:
TABLE 21-8:
RCON
OSCCON 0742
Legend:
Note
FOSC
FWDT
FBORPOR F80004
FBS
FSS
FGS
FICD
Legend:
Note
Name
SFR
Name
1:
1:
2:
Addr. Bit 15
0740 TRAPR IOPUWR BGST
Address
F80000
F80002
F80006
F80008
F8000A
F8000C
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Reserved bits read as ‘1’ and must be programmed as ‘1’.
TUN3
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
FWDTEN
MCLREN
BKBUG
Bit 15
FCKSM<1:0>
—
—
—
Bit 14
TUN2
Bit 14
COE
Bit 13
—
—
—
—
—
COSC<1:0>
Bit 12
Bit 13
—
—
—
—
—
—
Reserved
Reserved
Bit 11
TUN1
Bit 12
(2)
(2)
—
—
—
—
—
Bit 10
TUN0
Bit 11
—
—
—
—
—
—
—
Bit 9
NOSC<1:0>
(1)
PWMPIN
Bit 10
Bit 8
—
—
—
—
—
—
(1)
EXTR
Bit 7
POST<1:0>
HPOL
Bit 9
—
—
—
—
Reserved
FOS<1:0>
SWR
Bit 6
Reserved
LPOL
Bit 8
(2)
—
—
—
SWDTEN
LOCK
Bit 5
(2)
BOREN
Bit 7
—
—
—
—
—
—
WDTO
Bit 4
—
Bit 6
—
—
—
—
—
—
—
SLEEP
Bit 3
CF
Bit 5
—
FWPSA<1:0>
—
—
—
—
BORV<1:0>
IDLE
Bit 2
—
LPOSCEN OSWEN Depends on Configuration bits.
Bit 4
—
—
—
—
—
Bit 1
BOR
Bit 3
—
—
—
Bit 0
POR
Reserved
Depends on type of Reset.
Bit 2
FWPSB<3:0>
—
—
Reserved
Reserved
FPR<3:0>
(2)
Reset State
(2)
(2)
Bit 1
GCP
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0