DSPIC30F4012T-20E/SO Microchip Technology, DSPIC30F4012T-20E/SO Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F4012T-20E/SO
• Description: IC DSPIC MCU/DSP 48K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012T-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F4011/4012
10. Output Compare Module
11. INT0, ADC and Sleep Mode
12. 8x PLL Mode
13. 10-bit ADC: Sampling Rate
14. Quadrature Encoder Interface (QEI) Module
15. Sleep Mode
16. I
17. Motor Control PWM – PWM Counter Register
18. I/O Port – Port Pin Multiplexed with IC1
DS80215K-page 2
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero.
If 8x PLL mode is used, the input frequency range
is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
The 10-bit Analog-to-Digital Converter (ADC) has
a maximum sampling rate of 750 ksps.
The QEI module does not generate an interrupt in
a particular overflow condition.
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
The I
operating as an I
PTMR does not continue counting down after
halting code execution in Debug mode.
The Port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
2
C™ Module
2
C module loses incoming data bytes when
2
C slave.
19. I
20. Timer Module
21. PLL Lock Status Bit
22. PSV Operations
23. I
24. I
25. I
The following sections describe the errata and work
around to these errata, where they may apply.
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
2
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
2
C module is enabled, the dsPIC
2
C module is configured as a 10-bit
2
C module is configured for 10-bit
C devices, the A10 and A9 bits may
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