DSPIC33FJ32MC204-I/PT Microchip Technology, DSPIC33FJ32MC204-I/PT Datasheet - Page 299

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: IC DSPIC MCU/DSP 32K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC204-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330017
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

R
Reader Response ............................................................. 302
Registers
 2009 Microchip Technology Inc.
AD1CHS0 (ADC1 Input Channel 0 Select ................ 209
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 207
AD1CON1 (ADC1 Control 1) .................................... 203
AD1CON2 (ADC1 Control 2) .................................... 205
AD1CON3 (ADC1 Control 3) .................................... 206
AD1CSSL (ADC1 Input Scan Select Low)................ 210
AD1PCFGL (ADC1 Port Configuration Low) ............ 210
CLKDIV (Clock Divisor)............................................. 108
CORCON (Core Control) ...................................... 24, 76
DFLTCON (QEI Control)........................................... 177
I2CxCON (I2Cx Control) ........................................... 187
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 191
I2CxSTAT (I2Cx Status) ........................................... 189
ICxCON (Input Capture x Control) ............................ 154
IEC0 (Interrupt Enable Control 0) ............................... 85
IEC1 (Interrupt Enable Control 1) ............................... 87
IEC3 (Interrupt Enable Control 3) ............................... 88
IEC4 (Interrupt Enable Control 4) ............................... 89
IFS0 (Interrupt Flag Status 0) ..................................... 80
IFS1 (Interrupt Flag Status 1) ..................................... 82
IFS3 (Interrupt Flag Status 3) ..................................... 83
IFS4 (Interrupt Flag Status 4) ..................................... 84
INTCON1 (Interrupt Control 1).................................... 77
INTCON2 (Interrupt Control 2).................................... 79
INTTREG Interrupt Control and Status Register....... 100
IPC0 (Interrupt Priority Control 0) ............................... 90
IPC1 (Interrupt Priority Control 1) ............................... 91
IPC14 (Interrupt Priority Control 14) ........................... 97
IPC15 (Interrupt Priority Control 15) ........................... 98
IPC16 (Interrupt Priority Control 16) ........................... 98
IPC18 (Interrupt Priority Control 18) ........................... 99
IPC2 (Interrupt Priority Control 2) ............................... 92
IPC3 (Interrupt Priority Control 3) ............................... 93
IPC4 (Interrupt Priority Control 4) ............................... 94
IPC5 (Interrupt Priority Control 5) ............................... 95
IPC7 (Interrupt Priority Control 7) ............................... 96
NVMCON (Flash Memory Control) ............................. 59
NVMKEY (Nonvolatile Memory Key) .......................... 60
OCxCON (Output Compare x Control) ..................... 157
OSCCON (Oscillator Control) ................................... 106
OSCTUN (FRC Oscillator Tuning) ............................ 110
P1DC2 (PWM Duty Cycle 2)..................................... 171
P1DC3 (PWM Duty Cycle 3)..................................... 172
PDC1 (PWM Duty Cycle 1)....................................... 171
PLLFBD (PLL Feedback Divisor).............................. 109
PMD1 (Peripheral Module Disable Control Register 1) ..
PMD2 (Peripheral Module Disable Control Register 2) ..
PMD3 (Peripheral Module Disable Control Register 3) ..
PTCON (PWM Time Base Control) .......................... 162
PTMR (PWM Timer Count Value)............................. 163
PTPER (PWM Time Base Period) ............................ 163
PWMxCON1 (PWM Control 1).................................. 165
PWMxCON2 (PWM Control 2).................................. 166
PxDTCON1 (Dead-Time Control 1) .......................... 167
PxDTCON2 (Dead-Time Control 2) .......................... 168
PxFLTACON (Fault A Control).................................. 169
PxOVDCON (Override Control) ................................ 170
PxSECMP (Special Event Compare)........................ 164
QEICON (QEI Control).............................................. 175
RCON (Reset Control) ................................................ 64
115
116
117
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
Preliminary
Reset
Reset Sequence ................................................................. 71
Resets ................................................................................ 63
S
Serial Peripheral Interface (SPI) ....................................... 179
Software Reset Instruction (SWR)...................................... 69
Software Simulator (MPLAB SIM) .................................... 229
Software Stack Pointer, Frame Pointer
Special Features of the CPU ............................................ 211
SPI Module
Symbols Used in Opcode Descriptions ............................ 220
System Control
T
Temperature and Voltage Specifications
Timer1 .............................................................................. 145
Timer2/3 ........................................................................... 147
Timing Characteristics
Timing Diagrams
Timing Requirements
SPIxCON1 (SPIx Control 1) ..................................... 181
SPIxCON2 (SPIx Control 2) ..................................... 183
SPIxSTAT (SPIx Status and Control) ....................... 180
SR (CPU Status) .................................................. 22, 76
T1CON (Timer1 Control) .......................................... 146
T2CON Control)........................................................ 150
T3CON Control......................................................... 151
UxMODE (UARTx Mode) ......................................... 194
UxSTA (UARTx Status and Control) ........................ 196
Illegal Opcode....................................................... 63, 70
Trap Conflict ......................................................... 69, 70
Uninitialized W Register ....................................... 63, 70
CALLL Stack Frame ................................................... 48
SPI1 Register Map ..................................................... 41
Register Map .............................................................. 46
AC..................................................................... 240, 272
CLKO and I/O ........................................................... 243
10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
12-bit ADC Conversion (ASAM = 0, SSRC<2:0> = 000)
Brown-out Situations .................................................. 69
External Clock .......................................................... 241
I2Cx Bus Data (Master Mode) .................................. 259
I2Cx Bus Data (Slave Mode) .................................... 261
I2Cx Bus Start/Stop Bits (Master Mode)................... 259
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 261
Input Capture (CAPx) ............................................... 249
Motor Control PWM .................................................. 251
Motor Control PWM Fault ......................................... 251
OC/PWM .................................................................. 250
Output Compare (OCx) ............................................ 249
QEA/QEB Input ........................................................ 252
QEI Module Index Pulse........................................... 253
Reset, Watchdog Timer, Oscillator Start-up Timer and
SPIx Master Mode (CKE = 0) ................................... 254
SPIx Master Mode (CKE = 1) ................................... 255
SPIx Slave Mode (CKE = 0) ..................................... 256
SPIx Slave Mode (CKE = 1) ..................................... 257
Timer1, 2, 3 External Clock ...................................... 246
TimerQ (QEI Module) External Clock ....................... 248
ASAM = 0, SSRC<2:0> = 000)......................... 267
ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> =
00001) .............................................................. 267
266
Power-up Timer ................................................ 244
DS70283G-page 299